MN3101 math

[puppiesonacid]

I'm looking at the datasheet and the relationship between OX1, OX2 and OX3 and understand that the frequency is half the oscillator value.


So i do i determine the oscillator value based on the three values?

I know its a simple solve for x kind if algebra question but i suck at the math.

Looking at various clock circuits, it seems like there is an inverse relationshio between the cap value and the pair of resistor values. i.e. when cap value is high (220pf) resistor values are low values (47k&56k) but others have say a 33pf cap value with 180k and 220k. i get that it is also depended on the chip being clocked(BBD in my explorations).

I want to know how to calculate the clock and manipulate the values to explore the sounds produced by different clocking times.

Thanks!

Tony

[Vivek]

The specification sheet has a graph of frequency versus components.


http://experimentalistsanonymous.com/diy/Datasheets/MN3101.pdf


The oscillation frequency depends upon the values of R1, R2 and C1.

OX1 is name of a pin on the IC.

There are other modern PLL chips that could be used for the same application.



The frequency of the clock of the MN3101 does not change based on the BBD connected to it.

The behavior of the BBD changes based on the clock frequency fed to it.

[puppiesonacid]

right, i see that. im wondering what the formula for plotting those results is. i assume the values of the two resistors dont matter so long as they sum to the resistance in the x axis? but i want to know what the "right" cap value should be also. or am i just dumb and its staring me right in the face? like i said, looking at different clock schematics for the same chip across different circuits, the 3 values differ and ive noticed an inverse relationship. when cap value is high, resistor values are low and vice versa. is it 6 of one half a dozen of the other and the net results all wind up being the same? Because just increasing the cap value works to lengthen the delay to a point but then the value of the cap gets high enough that the clock noise/whine/ring bleeds through when the delay pot is at its longest setting. I would assume this occurs  if the other two values arent adjusted in relative proportions to the cap value change. but i have a feeling i might be wrong and simply need more delay stages.

i see that with both resistors being equal value (22k) you can go from 200pf to 100pf and shift the capacitive load(raise the frequency of the clock signal)

i want to play with the full range that the chip can handle (10 - 100) but find the best values in hopes of reducing or eliminating clock bleed. or is it only LPF that will offset clock noise? it seems that if clocked at the "right" frequency and corresponding values i should be able to shift the delay range lower(extend delay time)  and avoid increasing clock noise.

[Vivek]

The x axis is R2. It is not R1+R2

There is no constraint that R1 should equal R2

There is an user manual of some ancient chorus/delay on the net.

It showed additional pots on the outputs of the BBD, adjustments with oscilloscope to reduce clock noise by mixing the 2 outputs in correct way.

Normally you would have a variable resistor on the clock, with 2 or 3 caps that can be switched in, and that could cover a major part of the clock range

[PRR]

...I know its a simple solve for x kind if algebra question but i suck at the math. ...

They knew that. So they gave you math-free graphs. Just read-off working numbers.

[PRR]

...so long as they sum to ....

They do not "sum". R1 and R2 do different things.

R1 terminates in the infinite impedance of a CMOS input and "does nothing'. Infinity plus 22k is still infinity. However dumping a large C1 into CMOS input may blow the gate. So if C1 is more than 33pFd, they want you to put in a couple dozen K-ohms protection.

R2 is the timing resistor. There's minor added resistance in the CMOS but for most practical cases the frequency is inverse to R2*C1.

[puppiesonacid]

thanks! R2*C1 sure... i see there is a relationship between those components...how do you actually do the math though? the chart makes sense to a point, still it doesnt chart out what cap value to use in combination with any value of R1 and R2. do you pick the cap value first and then solve for R2? vice versa? trick question yourself by throwing R1 in just to see if you really know what you're doing haha?

im looking at it thinking "ok, two resistors and a cap, the right combo of values should give me X frequency" which is why i assumed the value of r1 and r2 summed to the total values given on the x axis. infinite theory aside, you usually or have two resistors and a cap(at least for any circuits im currently looking at). sticking with that configuration...what would be the formula to select a preselected clock frequency within the range the bbd can be clocked at?

or literally just throw r1 out the window, forget its there, it does nothing important, why did they put it there,  leave as is and just focus on R2*C1?

again...i dont get  how to multiply  a resistor by a capacitor. at first thought,  that seems like multiplying apples by oranges. help me to understand...

[Rob Strand]

right, i see that. im wondering what the formula for plotting those results is. i assume the values of the two resistors dont matter so long as they sum to the resistance in the x axis? but i want to know what the "right" cap value should be also. or am i just dumb and its staring me right in the face? like i said, looking at different clock schematics for the same chip across different circuits

It's complicated because the part of the timing (charge and discharge of C) involves C charging/discharging through R1 in parallel with R2.   When voltage on the cap is discharged to the point where the lower end of the cap is below the supply voltage the charge/discharge only involves R2.

Take look at the schematic of the oscillator on page 3 (page 60),
http://experimentalistsanonymous.com/diy/Datasheets/MN3101.pdf

R1 connects the input of the inverter.   Normally when you connect to an input the resistor has no effect.  However, in reality there's protection diodes at the input.  When the output at OX3 changes state the voltage on the lower cap terminal rise above and below the supply rails.   When that happens the input diodes at OX1 conduct and that causes a more rapid charge/discharge through R1 (R2 also contributes).    When C discharges enough there is no longer any charge/discharge through R1 and the charge/discharge slows down and only involves R2.

The diode drops further complicate the calculations and they make a small difference at lower voltages.

If you look at the timing plots you can see the clock frequency drops as you increase R1.    That's because it is slowing down the first part of the charge/discharge through the diodes and relying more on R2.   When R1 is very large the timing mostly depends on R2.    For high frequencies, oscillators like this won't work with the large resistor values because the input capacitance of the inverters will affect the way the oscillator works.

In order to calculate the timing you need to calculate the two parts of the discharge curve (it's actually four parts two for charge and two for discharge).   You can allow for diodes as well but it makes the equations a little messier.   So yes you can come-up with equations.

[puppiesonacid]

ok, thank you for the nuts and bolts explanation. i get the hesitance better now. i get why its not "that" easy to provide a straight answer.

well, i guess i'll stick to the values specified with the datasheet range  and then scope it to see what the period is? as if i really know how to execute that yet haha. i'll try to figure it out.

thanks again guys!

stay safe and take care,

Tony

[anotherjim]

R*C is not apples*oranges.
You are dealing with time.
The units all have linked definitions and the Farad is linked to the Coulomb which is linked to amperes and time. Resistance is linked to the ampere and controls the charge/discharge rate of C so R*C magically gives you the time in seconds.

[Rob Strand]

R*C is not apples*oranges.
You are dealing with time.
The units all have linked definitions and the Farad is linked to the Coulomb which is linked to amperes and time. Resistance is linked to the ampere and controls the charge/discharge rate of C so R*C magically gives you the time in seconds.

All RC oscillators are like that but it doesn't help get an answer.   You need to do an analysis and go through the calculations.

We already have the answer,  it's in the graph, but it's not presented as a formula.   The form the answer takes is outlined in my post.  From my outline, if we take the period of the oscillator as T,  the formula for T will be of the form,

T  = k1 * C * (R1 // R2)  + k2 * C * R2

An analysis would give formulas for k1 and k2.   However, if we try to apply that form of the equation to the graph it doesn't quite work - probably because the diodes have input resistance or there is an ohmic path on the input of the gate.

To cut a long story short if we use this formula, which adds series resistance between the gate input and diodes,

T  = k1 * C * (R1' // R2)  + k2 * C * R2

we can match the datasheet graph with,

k1 = 3.54
k2 = 3.70
R1' = R1 + 35000

So take the case with C = 100pF, R1 = 22k, R2 = 20k.
The graph shows about 80kHz, or T = 12.5us.  (freq = 1/T)

R1' = 22000 + 35000 = 57000
R2 = 20000
R1'//R2 = 1/(1/57k + 1/20k) = 14800

T = 100e-12 * (3.54 * 14800 + 3.7 * 20000) = 12.6us

So not a bad estimate.   I suggest trying other values it should be within about +/-10%.

The point where this formula starts to fail is at high frequencies.  This is where the graph in the datasheet starts to curve.
Some of that comes from switching delays in the inverter gates.

EDIT:
I remembered this old applications note from National Semiconductors,



It gives some simplified formulas but they don't seem to agree with the above.  These translate to T = 2 RC.
From what I can see the formulas above match the MN3101 datasheet.

OK, I think I know where discrepancy is.  The MN3101 divides down the raw oscillator frequency.
Presumably the graphs are for the MN3101 output.

[puppiesonacid]

R*C is not apples*oranges.
You are dealing with time.
The units all have linked definitions and the Farad is linked to the Coulomb which is linked to amperes and time. Resistance is linked to the ampere and controls the charge/discharge rate of C so R*C magically gives you the time in seconds.

thanks jim. i see what you mean. i really do appreciate you laying that out.

[ElectricDruid]

Getting the clock frequency is in some ways not the important bit. You mentioned a 'scope, so you could just measure the clock frequency.

What's more important is how much delay that gives you. The equation for that is:

   Delay in seconds = Number of BBD stages / (2 x Clock Frequency in Hertz)

So taking a MN3007 clocked at 100KHz as an example:

   Delay = 1024 / 2 x 100000 = 0.00512 = 5.12msecs

HTH.

[puppiesonacid]

R*C is not apples*oranges.
You are dealing with time.
The units all have linked definitions and the Farad is linked to the Coulomb which is linked to amperes and time. Resistance is linked to the ampere and controls the charge/discharge rate of C so R*C magically gives you the time in seconds.

All RC oscillators are like that but it doesn't help get an answer.   You need to do an analysis and go through the calculations.

We already have the answer,  it's in the graph, but it's not presented as a formula.   The form the answer takes is outlined in my post.  From my outline, if we take the period of the oscillator as T,  the formula for T will be of the form,

T  = k1 * C * (R1 // R2)  + k2 * C * R2

An analysis would give formulas for k1 and k2.   However, if we try to apply that form of the equation to the graph it doesn't quite work - probably because the diodes have input resistance or there is an ohmic path on the input of the gate.

To cut a long story short if we use this formula, which adds series resistance between the gate input and diodes,

T  = k1 * C * (R1' // R2)  + k2 * C * R2

we can match the datasheet graph with,

k1 = 3.54
k2 = 3.70
R1' = R1 + 35000

So take the case with C = 100pF, R1 = 22k, R2 = 20k.
The graph shows about 80kHz, or T = 12.5us.  (freq = 1/T)

R1' = 22000 + 35000 = 57000
R2 = 20000
R1'//R2 = 1/(1/57k + 1/20k) = 14800

T = 100e-12 * (3.54 * 14800 + 3.7 * 20000) = 12.6us

So not a bad estimate.   I suggest trying other values it should be within about +/-10%.

The point where this formula starts to fail is at high frequencies.  This is where the graph in the datasheet starts to curve.
Some of that comes from switching delays in the inverter gates.

EDIT:
I remembered this old applications note from National Semiconductors,



It gives some simplified formulas but they don't seem to agree with the above.  These translate to T = 2 RC.
From what I can see the formulas above match the MN3101 datasheet.

OK, I think I know where discrepancy is.  The MN3101 divides down the raw oscillator frequency.
Presumably the graphs are for the MN3101 output.

Rob! now THAT is reverse engineering my man! Talk about separating the men from the boys haha. Thank you for seeing my desire to really try to get educated on this subject. This is literal einstein stuff, the physics involved are astounding.  i will digest this and follow up with any questions. thanks again for your patience!

Getting the clock frequency is in some ways not the important bit. You mentioned a 'scope, so you could just measure the clock frequency.

What's more important is how much delay that gives you. The equation for that is:

   Delay in seconds = Number of BBD stages / (2 x Clock Frequency in Hertz)

So taking a MN3007 clocked at 100KHz as an example:

   Delay = 1024 / 2 x 100000 = 0.00512 = 5.12msecs

HTH.

Tom, thanks again for your help. Yes, i grasped that part i believe. it was The output frequency of the clock  is half the oscillator value statement in the datasheet that made me ask "ok well how do i know what to set the values for to get the desired frequency?"  and "what the relationship between the 3 variables is to create the oscillator and achieve any frequency between the 10kHz-100kHz stated that the chip can operate with." i stead of flying blind changing values.

[Vivek]

I found in listening tests,

A "Doubler / Chorus" with average delay of 10ms sounds pretty much the same as one with 12ms average Delay

hence it appears there is less need for exactitude of frequency (As long as you are in a particular range, you are fine)

Therefore a standard value cap of approximately the calculated / extracted from graph value is just fine

and you would normally adjust delay with a variable pot for R2


The Clock would look like the scope below :

[anotherjim]

You don't always get what the formula says anyway. Oscillators made from MOS logic will depend on the input threshold voltage that causes the output to switch high or low. Those threshold voltages are not a thing of precision and can vary with supply voltage. The threshold to a high switch can be different from the threshold to a low switch.
As frequency rises, the switching speed of the transistors adds delay that becomes more significant as the target frequency increases. If you need the timing capacitor sized in picofarads, the stray capacitance between the conductive parts becomes significant and also the input capacitance of the transistor gates. If you want a 22pF cap, the stray capacitance might be 3 to 6 ish extra pF!

The BBD clock output phases will be at half the clock oscillator frequency. To get the 2 phases a flip-flop will be used to get the alternating clocks the BBD system needs. The flip-flop will also enforce equal high/low (50% duty cycle) timing of the phases

[PRR]

All this was figured out decades ago. Why are we re-typing the wisdom of the ancients?

The guru for DIY CMOS is Don Lancaster. He has even put his CMOS Cookbook up for public use (I bought mine, several times).
https://www.tinaja.com/ebooks/cmoscb.pdf   10MB PDF file

Try (book) pages 269 to 273 (and more for further requirements).

[Rob Strand]

You don't always get what the formula says anyway. Oscillators made from MOS logic will depend on the input threshold voltage that causes the output to switch high or low. Those threshold voltages are not a thing of precision and can vary with supply voltage. The threshold to a high switch can be different from the threshold to a low switch.
As frequency rises, the switching speed of the transistors adds delay that becomes more significant as the target frequency increases. If you need the timing capacitor sized in picofarads, the stray capacitance between the conductive parts becomes significant and also the input capacitance of the transistor gates. If you want a 22pF cap, the stray capacitance might be 3 to 6 ish extra pF!

It boils down to what you use for C.   C can be the part value or C can be the total capacitance including the parasitics.   If the part itself has parasitic capacitances then some of those manufacturer's plots actually do include the parasitic capacitances.   Some deviation from general trends appear in the plots as well.  For example  the curvature of frequency vs R2 in the MN3101 data, which looks like gate delays to me.  There's not enough points for different capacitances to get parasitics from the MN3101 plots.

Tolerances are a different issue.  The basic formulas predict the design center and the tolerances and other variables predict the expected variations.

[puppiesonacid]

All this was figured out decades ago. Why are we re-typing the wisdom of the ancients?

The guru for DIY CMOS is Don Lancaster. He has even put his CMOS Cookbook up for public use (I bought mine, several times).
https://www.tinaja.com/ebooks/cmoscb.pdf   10MB PDF file

Try (book) pages 269 to 273 (and more for further requirements).

well, i guess by that logic no questions should be asked so long as you already know the answers

just having a conversation with some people who took the time to provide some better  insight and connect some dots.


its either a diy stomp forum community comprised of the knowledgeable and the uninitiate or its not.

thanks for the reminder on the lancaster book. forgot about that one. 

[Rob Strand]

well, i guess by that logic no questions should be asked so long as you already know the answers

It's a common problem.

There's no way the Lancaster book will know about 35 k ohm at the input of the MN3101 gate!   I was surprised to see such a high value myself.