Single op-amp LFO - I can't figure out what I'm missing

[R.G.]

I ran into something like this a a couple of releases of simulator ago. The final issue was that the simulator was setting all the initial conditions so the opamp was balanced at power on time and didn't have anything to kick start it.

Maybe try rigging a time delayed spike generator in your simulator if you can. My current simulator lets me tell it to leave the initial conditions on caps at zero, which nicely synthesizes the BANG! startup of turning on power in a real circuit. That always starts things that can oscillate.

[ElectricDruid]

+1 agree RG's point about initial conditions. I've hit that one a few times too.

I notice the op-amp says "741" on it, but does it have any supply voltages defined anywhere?

I had trouble simulating this same LFO in LTspice, and the problem there was that the "ideal" op-amps have no supply voltages, so they can put out infinite voltages - instead of a 9V square wave, the op-amp output was shooting off to tens of kVs!!

Also note that you don't *need* R9 and the Vbias. Those are for the FETs in the original phaser and the LFO runs fine without them.

[Jiminvan]

Thanks everyone. You're a great resource!  I switched to the "opamp with rails" model, and added a kicker to Vref to get things started, and now I'm seeing oscillation! 

See image attached (not sure how to embed right here amongst my text).

So now I'm seeing something like what I see in the actual circuit: the voltage being sent to the JFET gates (Vout) is being attenuated by the 3M9 and the 1M from the bias source, so it's only about 400mV p-p. That's not supposed to happen...right? It's not enough to swing the JFETs across the full range of channel resistance as desired...right?

Thanks again!
Jim

[Jiminvan]

Hi everyone: I'm left with a couple of questions on getting this to do what I think it is supposed to do in the Phase 90. 

I'm supposed to be able to get it to swing from 5.1V (Vgs = 0) to about 2-3V (Vgs = -2 to -3V depending on JFET pinchoff voltage), right?

But in the sim the cap voltage V(LFOtriangle) is only about 2Vp-p and by the time it hits the JFET side of the 3.9M resistor Vout is around 400mVp-p.  The only way I've found to get that to be more like it should be is to remove the bias network, or increase its 1M resistor to 5M or more, as it is forming a voltage divider with the 3.9M LFO output resistor. But I've not seen any Phase 90 circuits with anything other than 1M there. So I must be doing something wrong...?!

The other odd thing in the sim is that the rate control pot R1, at the standard 470k, is taking me from about 0.1Hz to 0.7Hz, and I know it's meant to get faster than that!

So all of this is making me question the Schmitt trigger thresholds the opamp is toggling at...maybe?  But this is the standard Phase 90 design, so I don't get it.

Thanks for whatever advice you can offer!

Jim

[ElectricDruid]

I don't know what voltages the JFETs in the Phase 90 are supposed to need, but I can confirm that my sim of the LFO produces about 2Vpp at the top of the cap too. And if you stick a 3.9M/1M divider on that, you're going to get about 400mV.

I don't agree about the frequency though. I've got a 470K pot and a 4K7 series resistor in my sim (with 15u cap). That gives 0.14Hz to 10Hz out of it, which seems very reasonable.

[Jiminvan]

Thanks for your reply @ElectricDruid. Your frequency results look more reasonable than mine for sure. I just remembered that I couldn't get the sim to oscillate with the rate pot at top speed so my previous results didn't go from 0 to 470k but ~100k to 470k.  I've fixed that now and with the pot at zero I'm getting around 10Hz as you are. Seems like a lot of the useful sweep is at one end, so maybe that's why the schematic I'm using has a C-taper pot in there.

My FET's need about a 2-3V swing in Vgs to go from full on to pinchoff (depending which ones I end up using). As it seems like the sim is behaving properly now (again big thanks to all of you), I'm left thinking its time to get back into real hardware. I'll put the FET's back in and remeasure everything in the actual circuit and see what Vgs swing I get. If it's too small I suppose I can play with the values of the 1M and 3M9 divider. Not sure what harm it would do given that the divider feeds JFET gates that don't load the divider at all.

Cheers,
Jim

[R.G.]

My FET's need about a 2-3V swing in Vgs to go from full on to pinchoff (depending which ones I end up using). 

That's the big issue - what do the real JFETs do when you solder them in?

My simulator sticks in a "typical" device for every semiconductor. This is what you usually need in a simulator, but on devices like JFETs, the relatively huge variations will fool the sim. I've tinkered in my sim with editing the device models to simulate device variance, but this gets limited by how much I can translate semiconductor parameters into what this does to Vgsoff and the change in Rds.

If I remember the circuit correctly, the originals were 2N5292 devices. I found that 2N5485 would work, and had a similar Vgs range, and they did seem to work in real hardware. I bought 100 of them and made a Vgs matching setup to find pairs and quads with similar Vgs at a given Rds.

Yeah, probably time for hardware.

[Jiminvan]

Hi RG.  I built and used your FET matcher for this!  Also another one that measured Idss and Vp. I couldn't get 2N5485's so I bought 4 each of the 2N5484's and J113's.

From your matcher with your stock 10k source resistor, the DMM readings for each set of 4 were surprisingly close, so I guess I got lucky given JFET variability:

2N5484's: -4.0V on all 4
J113's: -2.8V on all 4

I rounded out the 3rd digit because I doubt it's significant.  I'll socket and try both in-circuit and see what I get.

I do have another question for everyone though, please and thanks. The above values are from RG's matcher so that's essentially giving Vgs at Rds = 10k. The other tester measures Vgs with the gate grounded and a 1M resistor from source to ground, giving Vp. I thought that would give a lower (more negative) value than the Vgs(10k) readings but it didn't.  For the 2N5484's the Vp I got were all around -1.1V which is in range per their datasheet, but is higher than the Vgs(10k) readings of -4V or so. Something seems wrong...?! 

Thanks again everyone. This is a great source of  knowledge and support!

Jim 

[Rob Strand]

I do have another question for everyone though, please and thanks. The above values are from RG's matcher so that's essentially giving Vgs at Rds = 10k. The other tester measures Vgs with the gate grounded and a 1M resistor from source to ground, giving Vp. I thought that would give a lower (more negative) value than the Vgs(10k) readings but it didn't.  For the 2N5484's the Vp I got were all around -1.1V which is in range per their datasheet, but is higher than the Vgs(10k) readings of -4V or so. Something seems wrong...?!

You are correct.  RG's test is good for matching but the measured Vgs is at 450uA, so the magnitude of the measured |Vgs| is less than the actual |VP|.  With the matchers that use 1M and 10M the test current is lower so the measured Vgs is closer to |VP|.

I've mentioned this in a few posts in the past, here I give a correction factor.  However the correction factor is only an approximation so you can compare the measurements of RG's circuit with the other circuits:
https://www.diystompboxes.com/smfforum/index.php?topic=126611.msg1211420#msg1211420

For a precise correction you need to measure IDSS and use more exact formulas, but even then you will find it doesn't agree with the 1M test circuits either because of finer points of JFETs! 

It all depends if you want to *extract parameters* or  just match.

Something to be aware of is when you use 10M (or even 1M) the reading can be off because noise gets into the circuit and corrupts the Vgs measurement.   I posted some info on this in the past.  For the 1M test circuits I suggest adding 1uF across the meter terminals, or across the gate and source,  to reduce noise and adding a 1k in series with the gate to prevent oscillations or RF - it can make a big difference to the consistency of the measurements.

[ElectricDruid]

Don't forget that you can adjust the values of R4 and R5 to tweak the switching point and adjust the triangle level. 330K for R4 gives you about 2.8Vpp and 220K gives you about 3.5Vpp. Alternatively, reduce R5. It'll affect the triangle "triangleness" (it'll get more "shark's fin") and it'll change the frequency too (since it'll take longer to charge up before it switches direction) but those aren't impossible problems. You can certainly fix any frequency range problems by tweaking the cap and/or resistor and pot. The slight bendiness of the triangle you have to put down as "character" - try it in the sim and I think you'll agree it's not so bad, at least as far as I went. Obviously, the further you push it, the worse it gets.

If you've got JFETs that need a bigger swing, it might just get the whole thing running.

[Jiminvan]

Thanks again everyone. Lots to think about. I'll get out of the sim world and back into hardware this weekend!

[Eb7+9]

I rounded out the 3rd digit because I doubt it's significant

one significant digit is giving you +/- 50 mV error on Vgs(off)

which means that two devices could have Vgs(off) differ by up to 100mV and translate into the same single-digit value

the phase90 LFO sim that I posted in the sim section shows 300mVpp swing at the gates
100mV error is significant in relation

you want them starting "as close as possible" to the same place, or the phasor will sound sub-par



2-significant digit readings come with a +/- 5mV error, or 10mV span on Vgs(off)


this is where you start finding out "how much" of a match you're really getting ...

or not


bw, Vgs(off) only provides half the picture ... Idss has to coincide as well for "full" match


https://viva-analog.com/characterizing-and-matching-2n5457-jfet-transistors/

[R.G.]

bw, Vgs(off) only provides half the picture ... Idss has to coincide as well for "full" match

I think I hear violins - and an echo.   

[antonis]

bw, Vgs(off) only provides half the picture ... Idss has to coincide as well for "full" match

I think I hear violins - and an echo.   

Here we are, again..!!