Why am I getting better headroom?

[stonerbox]

Working on a simple JFET buffer stage (in LTSpice) that runs on 14V. 15k on drain, 10k on source and 1Meg pulldown on gate. It can take up to 1.2V, pass that and clipping in top part of the wave starts to form. However if I omit the 1M gate resistor the freaking thing can chew up to around 3V no problem before clipping occurs. Odd! Help me understand!

Edit: Never mind it is terrible practice to not bias.

[Digital Larry]

I probably don't know the answer, but does the output bias point shift?  I'm guessing obviously it did, but just want to be sure.  I presume the input is capacitively coupled?

[stonerbox]

That is correct. From 9V to around 13v. Gate goes from 4.5v to 0v, obviously.
I got 6.8n in and .1uF coming out.

I slapped it on a bb with the 1Meg omitted and it sounds fine! No noticeable noise either which is strange and it takes a 18 dB boost like a champ, slight coloration but still pretty clean in my opinion. What is going on here?

[PRR]

It's distorting. In a Hi-Fi world you would notice. E-guitar, maybe not.

Don't let the bias default to Vgs. Bring it up around 1/3rd to 1/2 for a follower, you get close to 3Vrms with any JFET.

[iainpunk]

what you have there isnt a buffer, but a gain stage with a gain of -1.5x (3.5db).

if you want that gainstage to work, you should try and find the optimal DC operating point, which is about 9.5v on the collector. drain.
the Gate voltage should be near 3v.

cheers

[PRR]

what you have there isnt a buffer, but a gain stage with a gain of -1.5x (3.5db)

I see.

....the Gate voltage should be near 3v.

It probably won't be happy at 3V on Gate. That may be 4V on source resistor. The drain resistor being 1.5X bigger will be dropping 6V. And we need a volt or two drain-source. We don't have 12V to play with under a 9V battery.

[stonerbox]

what you have there isnt a buffer, but a gain stage with a gain of -1.5x (3.5db)

I see.

....the Gate voltage should be near 3v.

It probably won't be happy at 3V on Gate. That may be 4V on source resistor. The drain resistor being 1.5X bigger will be dropping 6V. And we need a volt or two drain-source. We don't have 12V to play with under a 9V battery.

Not happy at all! Performance is at its best at 0.2v on gate, 0.79 source and 9v on drain.

Shameful update... on the far side of the board sat some components that acted as pulldown(s) on my gate. Sounds awful without them, a 1Meg pulldown or a VD. Magic demystified.

But I still can not help but wonder why LTspice presents a cleaner signal (yes, it is still visibly affected in top and bottom part of the wave) and larger swing when the pulldown is removed?

[Rob Strand]

What you will find is it is re-biasing the JFET.   Open gate won't always give the best result.

Better is rebias the JFET using a more normal scheme.   

Try adding a positive bias scheme to the gate, like the 100k + 10k network on the Sadowsky preamp
https://www.diystompboxes.com/smfforum/index.php?topic=119310.msg1112690#msg1112690

With your circuit values I suspect a 100k + 22k or 100k + 27k bias network will bias more favorably.

Remember, watchout over optimizing JFET circuits in spice as the real JFET you put in the circuit
will be different to the model and the optimum bias point might need a slightly different resistor.

[stonerbox]

-Remember, watchout over optimizing JFET circuits in spice as the real JFET you put in the circuit
will be different to the model and the optimum bias point might need a slightly different resistor.

Very true.

I ended up using 820k from rails and 15k to ground (0.2v). Will this suffice, it sound good, or are the VD+resistor and cap biasing a better choice?

[Rob Strand]

-Remember, watchout over optimizing JFET circuits in spice as the real JFET you put in the circuit
will be different to the model and the optimum bias point might need a slightly different resistor.

Very true.

I ended up using 820k from rails and 15k to ground (0.2v). Will this suffice or are the VD+resistor and cap biasing a better choice?

Adding 15k to ground will lower the input impedance quite a bit.  The advantage of the VD+resistor and cap  is you can keep the high impedance by using a 1M back to the voltage divider.   It also lets you filter the divider.   Disadvantage is more parts.

I had a look at the biasing maybe around 100k+18k and 100k+20k is better.

That's quite a bit different to the 820k + 15k values you got.

[iainpunk]

what you have there isnt a buffer, but a gain stage with a gain of -1.5x (3.5db)

I see.

....the Gate voltage should be near 3v.

It probably won't be happy at 3V on Gate. That may be 4V on source resistor. The drain resistor being 1.5X bigger will be dropping 6V. And we need a volt or two drain-source. We don't have 12V to play with under a 9V battery.

it should have said 3v on the source, not the gate, oops

in the original post, he noted he was running a 14v system, thats where i based those voltages on.

cheers