Jfet bias issue, what I am doing wrong?

[percyhornickel]

Hi, I am trying to set the right midpoint bias (Vd = 4.5V) of some Jfets I have in here with no luck until now.  (Typical self bias circuit)

* With the Runoffgroove Jfet tester values for 2SK68A Jfet: (on the breadboard)

Vcc = 9V

Idss = 6,60mA
VTO = -1,16V

* Calculating voltages:

Vcc = 9V
Id = Idss/2 = 3.30mA
Rd = 4.5V/Id = 1.37K
Rs = Vgs/Id = 100 Ohm
Rg = 1M

For Vd the value expected was 4.5V, but after breadboarding the circuit I am reading 5.37V.

Even, I have used Lt Spice and simulated the circuit and the jfet model and the result is Vd = 4.5V too.

Lt Spice jfet model used:
               
.model K68A NJF(Vto=-1.16 Beta=4.9m) ; Beta = Idss/VTO^2


I´d tried to set the midpoint bias of 2N5458 too and the problem is the same, the Vd is higher than the calculated value.

What I am doing wrong with my calculated values?, why the real Vd is so different?


Thank you.



Percy

[PRR]

...expected was 4.5V, but .. I am reading 5.37V.

I doubt that matters. But try changing the 100r to 82r. Is that going in the right direction?

[Rob Strand]

For some JFETs extracting VP using the test jig doesn't always give the best model when the JFET is used at significant current, for example when used as an amplifier.  There's also other factors, see,
https://www.diystompboxes.com/smfforum/index.php?topic=126702.msg1243138#msg1243138

At the end of the day, parts are what they are and will do what they will do.  If you want 4.5V at the drain just adjust Rd to make it so.  Maths/models get you close, as you have done already, but reality is reality.

If you want to know why the maths/models isn't as close as you expected then that's a whole different investigation.  With some effort you can work out where things have gone wrong.

[diydave]

I'm not a fan of the fetzervalve method off calculating Rd. It's confusing.
What I do to bias a fet is the following:
1) measure Vp:
connect drain to Vss and gate to Ground. set multimeter to mV and measure the voltage between source and ground. That's Vp off your fet.
2) measure Idss:
connect gate and source to Ground. set multimeter to mA and measure the current between drain en Vss going through your multimeter. That's Idss.

I like to have the inputswing at the gate mid Vp. That way my inputsignal doesn't get clipped, or it gets clipped top and bottom evenly. That's your Vgs.
Now you know all your parameters, except the appropriate Id for your selected Vgs.
So we'll calculate it:
Id = Idss(1-(Vgs/Vp))²

Since we now know Id, we can calculate Rs=Vgs/Id.
To have a voltagedrop of 4.5v over Rd, Rd=4.5v/Id.

Years back, I've made a calculator to do the hard work.
It calculates 10 Vgs voltages, with the accompanying Id, Rs and Rd.
https://www.diydave.be/tools/fetcalc/index_eng.html
I still use it.

[percyhornickel]

PRR,  almost the same with 82r, not that exactly as I was expecting for.

Rob, yes maybe I need to start thinking jfets are not as perfect as I thought. I´ve been studyng deeply a good way to model jfets in spice...   and yes, theory and reality are not the same.

diydave, I haven´t seem the jfet bias site. Great tool, until now I used excel to generate the transconductance graph according the literature I have read in some books, dos, pdf, webs, etc.
I get the same values so theorically I think I was in the right path.

I think I tried before that way to get Idss and Vto with no big diference, I really don´t remember so I hope to have time today to testthe jfets just right with the DMM and compare the values with the runoffgroovetester.

Thank you all for your replys, let´s see what I get now...   ...I´ll be making some tests.



Percy

[antonis]

FWIW, Drain (Collector) mid-supply bias is symmetry effective only for grounded Source (Emitter)..
In case of Source (Emitter) resistor, V_D should be at (V_CC + V_S(E)) / 2

Actually, even a little bit higher due to both non-static Source (Emitter) voltage (going up when Drain (Collector) is going down) and R_DS(ON) (V_CEsat)

[Vivek]

Two articles re FET modelling in SPICE that may be pertinent

http://preamp.org/static/adventures-in-spice-real-life-transistor-parameter-variation/index.html

http://www.ece.mcgill.ca/~grober4/SPICE/SPICE_Decks/1st_Edition_LTSPICE/chapter5/Chapter%205%20MOSFETs%20web%20version.html

[Rob Strand]

Rob, yes maybe I need to start thinking jfets are not as perfect as I thought. I´ve been studyng deeply a good way to model jfets in spice...   and yes, theory and reality are not the same.

One test is to put the test jig into spice and see if the simulation of the test jig together with the JFET+model parameters produces the same measurements.   Don't forget to include the DMM impedance (typ 1M ohm or 10Mohm but not always).

[percyhornickel]

Vivek, in the first article this guy did almost the same I did in LT Spice, first I generated the Id vs. VDS curves taking VTO, BETA using the datasheet medium values (Vgs off and Idss) and lambda (slope). For lambda I just increase the value until the slope was almost the same the datasheet graph.

I don´t know if I have to take the same lambda value for the same jfet with different Vto and Idss, Beta would be diferent too.

In any case, lambda doesn´t affect that much the final value as far as I can see.

I could replicate the datasheet graph with this method, I am sending some K68A images (circuit and graphics).

Taking the midpoint (Idss/2) and Vd 4.5V I get the same calculated values from the formulas but reality is different once I breadboard the circuit.


Datasheet medium values








Self bias circuit:

[percyhornickel]

Rob, yes maybe I need to start thinking jfets are not as perfect as I thought. I´ve been studyng deeply a good way to model jfets in spice...   and yes, theory and reality are not the same.

One test is to put the test jig into spice and see if the simulation of the test jig together with the JFET+model parameters produces the same measurements.   Don't forget to include the DMM impedance (typ 1M ohm or 10Mohm but not always).

Rob I think tht´s what I did, I did the maths, then the spice and the values were almost the same but once I put the circuit in the breadboard....    ...1 volt or more difference, I need to dig in this issue because is too much diference.

How do you think I could include the DMM impedance in the simulation?..   ...I just have a couple of years studing electronics like a hobbie but I am Petroleum Engineer.

[percyhornickel]

FWIW, Drain (Collector) mid-supply bias is symmetry effective only for grounded Source (Emitter)..
In case of Source (Emitter) resistor, V_D should be at (V_CC + V_S(E)) / 2

Actually, even a little bit higher due to both non-static Source (Emitter) voltage (going up when Drain (Collector) is going down) and R_DS(ON) (V_CEsat)

Antonis very interesting your comment, let me try to read better some of my docs..   ...I am just using the jeft self bias formulas with the drain resistor and I have seen many books doing the maths this way, please let me try to understand batter this way and maybe keep testing in here.

Percy

[antonis]

I am just using the jeft self bias formulas with the drain resistor and I have seen many books doing the maths this way, please let me try to understand batter this way and maybe keep testing in here.

It has nothing to do with textbook maths or so..

I was talking about "ideal" CS (CE) amp bias..

You see, mid-supply Drain (Collector) bias is symmetricaly effective only when Drain (Collector) can swing from V_CC to GND..
In case of Source resistor existence, Source sits at "some" voltage level, which level is furthermore raised for signal positive waveform at level almost equal to bias voltage plus signal amplitude..
In such a case, Drain can't go lower than that voltage level but it can comfortably go up to V_CC (ideally) for negative signal waveform..
(bye bye symmetry..)

P.S.
I didn't opposed your maths but your Drain bias point target..

[percyhornickel]

Antonis, is a kind of "virtual ground" the vd floating a some voltage level? maybe something like that hat you are talking about?.

What do you think is better for bias (Vd 4.5V), stick the source resistor (Id/Vgs) value according the transc graph and use a trim for Rs, or using a Drain resistor (4.5/Id) and using a trim for Rs?, of course Vcc 9V.

[antonis]

What do you think is better for bias (Vd 4.5V), stick the source resistor (Id/Vgs) value according the transc graph and use a trim for Rs, or using a Drain resistor (4.5/Id) and using a trim for Rs?, of course Vcc 9V.

I think, for the 3rd time, to bias Drain at level HIGHER than 4.5V..!!

Let's take it via an numerical example:

Consider a CS amp with 1mA working current, 4k5 Drain resistor and 1K Source resistor..
Drain is biased at 4.5V (mid-supply) and Source at 1V..
Amp exhibits a gain of approximately 4.5.. (R_D/R_S)

For a 1V_peak Gate signal, Drain can swing undistorted up to +9V (for signal negative waveform) but it will start distorting down to 2V (for signal positive waveform) 'cause there is 1V signal added on already existing 1V bias on Source..

So, we have 2.5/4.5 swing around Drain bias point..
That's no symmetry..

P.S.
IMHO, first things you have to consider for a single CS amp is Drain resistor (for setting output impedance), working current (for setting Drain at particular voltage level) and power supply..
Al the others will occur via graphs and formulas..

[percyhornickel]

Antonis for the 3rd time thank you     

Great and easy explanation for easy understanding.!!!!