MFC4040

[Rob Strand]

I was doing more research on 4013 dividers, and lo and behold, I came across Fredrik's Parasit Studio site. He has a page covering just this stuff. Funny enough, in his experiment project, he states that there should be a 10k resistor between the 2 and 5 pins. I found this curious, since every other schemo I've looked at to date shows a direct connection. Anywho, I connected pins 4 and 6 to ground, as they should be, and replaced the 2 and 5 jumper with a 10k resistor.

Yes it's not normal.  What it might do is block glitches.    There is capacitance on the input of the 4013 (natural occurring  ).   If there was a stable voltage on the output of the /Q pin then that capacitance will charge via the 10k.   When the clock comes along the capacitance holds the correct D input for the output to toggle.  However, if the clock glitches immediately after that the capacitance hasn't had time to change state and still holds the old value, then it clocks through the correct D value effectively ignoring the glitch!   It's double clocking but with the illusion that all is OK because the overall toggle is correct.

https://www.parasitstudio.se/building-blog/cmos-workshop-part-3-octave-down

You can see a more deliberate use of capacitors to block clock pulses occurring too close to the initial clock pulse in this circuit.   It's kind of a blanking period.




My guess is the need for the 10k's indicates a problem that shouldn't be there.

FWIW, from what I can see the two transistor "flip-flop" Q43, Q44 doesn't act as a flip-flop as such, hence why it is different from the Boss footswitch flip-flop.   It seems to work like a switch.   I was thinking what does it add?  Perhaps nothing in itself but it allows the pulse network C44 & diode to perhaps block glitches.  Unfortunately there's still the possibility of deeper level glitches around the 4013 and the Q43/Q44 circuit cannot help those.

[digi2t]

Might be just the fact that the chip is on the breadboard, and I have jumpers going between it and the board. Lots of antennae there for stray capacitance I guess. I see from the schemo you posted that the 2k2 and 100n are acting as filters?

That Parasit Studio page is the one I was talking about. That's where I saw the 10k between the /Q and data pins. As soon as i did that, it sprang to life.

Once the 4013 is on the board, it may help eliminate the glitching, but I think I'll have a spot for that resistor (and maybe a cap too?) available, just in case.

That's it for tonight. Tomorrow I attack the envelope. Probably something dead stupid.

[Rob Strand]

Might be just the fact that the chip is on the breadboard, and I have jumpers going between it and the board. Lots of antennae there for stray capacitance I guess. I see from the schemo you posted that the 2k2 and 100n are acting as filters?

Well they are filters but what they are really doing is serving as "memory" to hold the D input to the correct value for a short time after the clock.  Essentially filtering in time.

(Without the caps) The basic idea of the circuit is the Q (and /Q) output toggles on each clock, hence the divide by 2.    The way it works is when the Q output is high, the /Q output is low.   /Q connects to D which is currently low.  When you issue a clock the D input is transferred to the Q output, in this case Q becomes low.   Now the Q output is low, /Q is high, D is high.  If you get a second clock the D which is high gets transferred to Q.  So you can see Q continually toggle.

In theory no matter how quickly the clock pulses occur the output will toggle.    If the clock glitches (think of ns time scale) on each clock you get multiple toggles of Q in a very short space of time.   After all that glitching is finished the Q output can be at a random state.  On the larger time scale of music signals, say 2ms, there is no evidence of the toggling to give you a divide by 2.

What the capacitor does on the D input (which in the 10k case is the capacitance of the chip) is hold the D input to the old value.   It will hold the input for a short time dependent of the resistance and capacitance values.   Suppose we say the highest input frequency is 20kHz, that's 50us.    Suppose we chose the resistance and capacitance to hold up for 50us.

Now, imagine the Q output is high, the /Q output is low; same starting conditions are previous example.   Suppose the /Q output has been low for some time and it has charged the cap to a low voltage and that voltage goes to the D input.   We now get a clock pulse, as before the low value on the D input is transferred to the Q output and it goes low (ie. toggle).  But now suppose the clock is glitching on a small time scale after that,  a time scale smaller than 20us.  Because of the cap, the voltage on the D input hasn't had time to change to high yet, so when we get a spurious clock pulse  the chip transfers the low D value through to Q again.   From Q's perspective nothing has changed.  From the glitch's perspective the glitch has been ignored.  If the cap wasn't there the D value would have changed immediately the clock glitch would cause a false toggle, like the previous example.     So the cap and resistor give a way of ignoring clock pulses which we know are too close to the last one.   By too close we mean changing state quicker than music frequencies should change and that just happens to include glitches as glitches occur on a very short time scales.

[Govmnt_Lacky]

Well...

I was doing more research on 4013 dividers, and lo and behold, I came across Fredrik's Parasit Studio site. He has a page covering just this stuff. Funny enough, in his experiment project, he states that there should be a 10k resistor between the 2 and 5 pins. I found this curious, since every other schemo I've looked at to date shows a direct connection. Anywho, I connected pins 4 and 6 to ground, as they should be, and replaced the 2 and 5 jumper with a 10k resistor.

CAP'TIN... THERE BE SUB-HARMONIC HERE!!

It's not only working, but it's also copping the same performance of the original. So, consider this issue resolved. But, I would like to know what exactly that 10k resistor is doing. Knocking back the second output signal enough to keep it from glitching?

So now, the only outstanding thing is the envelope. Right now, when I turn it on, audio goes silent. I'm checking voltages now, and I see that the pins that should be flipping between 0v and 12v with transients, are not. This in turn, from the way I see the schemo, isn't sending any current to the 3080, so no attack and decay action. Already found one bum transistor in the sub-harmonic section, combing through this section now.

I'm sooooo close...