question about making a big muff with an jfet based input and output stage

[snow123]

Hey guys, I'm trying to make a big muff with a JFET based input and output stage (and might replace the BJTs for JFETs in the clipping stage), but I'm not sure how to go about it.

I tried breadboarding just the input stage but with a 2n5457 instead of a 2n5088 (or any other BJT), and it didn't work (as i figured), and i only hear my picks attack when I try playing with it. so I'm wondering what I need to change to make it work.

here's the schematic I'm working with right now, but everything is likely gonna change, and I've only breadboarded the input stage.

[antonis]

I tried breadboarding just the input stage but with a 2n5457 instead of a 2n5088 (or any other BJT), and it didn't work (as i figured), and i only hear my picks attack when I try playing with it. so I'm wondering what I need to change to make it work.

Change JFET bias configuration..

There was a similar project from Jack Orman, but I can't recall it right now..

[snow123]

I tried breadboarding just the input stage but with a 2n5457 instead of a 2n5088 (or any other BJT), and it didn't work (as i figured), and i only hear my picks attack when I try playing with it. so I'm wondering what I need to change to make it work.

Change JFET bias configuration..

how do i do that though?

[Kevin Mitchell]

Ah snow. The man, the myth, the legend.
Here's a little read on jfet biasing.

And welcome back!

[antonis]

how do i do that though?

May I ask the reason for altering Big Muff In & Out configurations..??

(or am I looking for land in trouble..??)

[snow123]

how do i do that though?

May I ask the reason for altering Big Muff In & Out configurations..??

I'm thinking it would give it a different sound. and I just want to experiment with JFETs in a big muff, starting with the input and output stage.

[antonis]

I'm thinking it would give it a different sound.

May I assure you for the opposite..?? 

P.S.
Be aware of oversights when copying schematics,,
(e.g. no ordinary BJT should work with that R20 value..)

[AdamM]

AMZ had the fet muff years ago... 4 jfet stages. It sounds great as I recall. Sadly I cannot find a schematic.

[snow123]

P.S.
Be aware of oversights when copying schematics,,
(e.g. no ordinary BJT should work with that R20 value..)

that was actually a typo lol, its supposed to be 100k.

[snow123]

so im assuming i change the value of R2 for it to work? 'cause i believe that resistor is what adjusts the bias for Q1.

[Kevin Mitchell]

AMZ had the fet muff years ago... 4 jfet stages. It sounds great as I recall. Sadly I cannot find a schematic.

I was curious about this one. Looks like it was pulled years ago.
But they did write a book that snow may very well enjoy! - probably why they pulled their schematics.
https://www.amazon.com/dp/B0749RW4Y6

[antonis]

so im assuming i change the value of R2 for it to work?

For a BJT, yes..

Did you read the link posted by Kevin..??
If yes, we would be happy to answer any possible query originated from there..

Or you're just hoping for a ready-to-race JFET configuration scheme posted by some willing guy..??

[anotherjim]

JFET gates don't usually need a positive bias voltage - it can be hard enough to get the source voltage high enough to get it biased.

[snow123]

so im assuming i change the value of R2 for it to work?

Did you read the link posted by Kevin..??
If yes, we would be happy to answer any possible query originated from there..

yes, I did read the link. I guess I'm not entirely sure what JFET biasing circuit in the link would match up best with the input booster I have set up rn.
But my understanding of it so far, is that R4 and R5 would set the biasing, is that correct?

[antonis]

But my understanding of it so far, is that R4 and R5 would set the biasing, is that correct?

Not quite..

R4 in conjunction with R2 set channel current I_D (current from +9V -> R5 -> Q1 -> R4 -> GND)
R2 serves to set a voltage level at Gate (usually near 0V)..
According to Drain desirable bias voltage and Drain resistor value (which sets stage's output impedance), there is a proper working current (I_D = (9V - V_D) / R5)
That current can be estimated by V_GS /I_D curve, so R4 value is set accordingly (V_S = I_D x R4) and V_GS (absolute value) is V_G - V_S..
Gain of stage roughly is R5/R4 but by shunting R4 to GND via a cap you increase it to g_m x R5..

[antonis]

Let's implement an hypothetical example..

R2 = 1M, R5 = 10k and I_D = 450μA for a V_GS = -1.75V
V_G is 0V (due to practically no current flow through R2 - take it as I say it for the time being)..
For a V_GS of -1.75V and I_D of 450μA, we need a R4 of 3k9..
(of course, gain only approaches to 2.5 but a R4 by-pass cap might be proved your friend..)

Now you're ready to choose your particular JFET, read its datasheet and make your own Common Source amp..

P.S.
In case of weird results after exact implementation of the above said, put the blame on JFET parameters wide spread and not on me...

[snow123]

Let's implement an hypothetical example..

R2 = 1M, R5 = 10k and I_D = 450μA for a V_GS = -1.75V
V_G is 0V (due to practically no current flow through R2 - take it as I say it for the time being)..
For a V_GS of -1.75V and I_D of 450μA, we need a R4 of 3k9..
(of course, gain only approaches to 2.5 but a R4 by-pass cap might be proved your friend..)

Now you're ready to choose your particular JFET, read its datasheet and make your own Common Source amp..

P.S.
In case of weird results after exact implementation of the above said, put the blame on JFET parameters wide spread and not on me...

Thank you!

[antonis]

Thank you!

You're welcome..

Just to confuse you a bit more:

It should be easier (IMHO) to implement self-biasing formulas, like I_D = I_DSS (1 - V_GS/V_P)², where I_DSS = Drain current for V_GS = 0 (considered device almost maximun current) and V_P = Pinch-off voltage (also found as V_GS(OFF))..
Both the above parameters can be found on datasheets (exhibiting a wide spread, of cource..)
Then you can proceed to proper sizing of Drain (R5) & Source (R4) resistors values for V_DS (Drain - Source voltage) and V_GS (the one contributed in I_D formula) via V_DS = 9V - I_D(R5 + R4) and V_GS = V_G - V_S = 0V - I_DR4..

Good luck..!!
(a pot, wired as variable resistor, in place of R5 might be your good luck charm..)

[anotherjim]

If you don't like math, the trendy thing to do is fit a trimmer pot as the drain resistor. Usually, 100k is shown, but to me, 50k should give easier tweaking. Adjust for the best sound although the drain voltage should come out anywhere 3v - 6v.
The gate resistor to 0v basically only sets the input impedance. 1M is usually fitted for guitar input but these distortions often have lower about 100k which tends to make it more mid focused.
The output stage loads the 100k tone pot and that could have a 1M gate resistor but the original BJT is more like 100k I think.

[m4268588]

One method not to use a trimmer pot.