Choosing resistor values for JFET audio switch

[jsoto]

I'm trying to design the on-off circuit / output stage of a mini-synthesiser I'm working on. My goal is to minimise bleed-through when the circuit is off. This is the design I have come up with, which I think works quite well:



I've also tried other configurations, but this one gives good results without having to add a whole lot of additional components (I was already going to use the two TL072 op-amps for the output stage anyway). I have considered using analog switches, but they tend to come in fairly large packages and I have limited space. I could also use an L-type configuration (adding a transistor to pull the signal to ground) but I would have to invert the signal. This configuration also allows me to buy only one JFET part to reduce costs (bulk order). I am using the 2N5457 for testing, but for the final design I plan to use a JFET with smaller (less negative) Vgs(off).

However, there must be room for improvement. If my understanding of JFET audio switches is correct, it would be best to scale down the JFETs input signals mainly for two reasons (please correct me if I'm wrong): on the one hand because it maximises off-Vgs and thus improves attenuation (in my design Q1 off-Vgs is -2.5V and scaling down the signal x10 it would be -4.3V), and on the other hand because it limits the on-Vgs variation and thus minimises distortion (although distortion is not my main concern since this mini-synth only produces square waves).

Based on the above, I suppose a design like this one should give better results:



The signal is scaled down x10 (400mV p-p) before Q1 and then scaled up x10 (4V p-p) at the second inveting op-amp (U1B). C6 value is modified just to maintain the same filter cutoff point.

To my surprise, this second design has even more bleed-through. I think the problem is the 100k pot (RV1). If I use a 10k pot instead, the circuit works fine and gives slightly better attenuation, but it also forces to use 1k for R8 which I guess is not ideal (as Q2's R-on becomes very significant). I've read that the larger the resistor the more sensitive it is to picking up capacitive noise (also, I'm doing all my testing on a breadboard, which doesn't help). Could this be the problem? In that case I guess a good PCB design could solve it. The other explanation I can think of is that, when increasing the U1B feedback resistor x10, Q2's R-off needs to be 10 times bigger to provide the same level of attenuation, and the extra attenuation achieved by increasing Vgs in this case is not enough to counteract this effect. Does this make sense?

[Rob Strand]

Just a quick answer:

This configuration also allows me to buy only one JFET part to reduce costs (bulk order). I am using the 2N5457 for testing, but for the final design I plan to use a JFET with smaller (less negative) Vgs(off).

Yes, that will help the off state quite a bit.

However, there must be room for improvement.

The cathodes of the diodes that go to the gates should be pulled up to +9V, not +5V.  That might help a bit.

If you have high Vgs_off JFETs you can bump your Vref up.  That will buy some margin in the off_state and lose some margin in the on-state.  You can only do this in small doses as changing Vref too much will eat into your signal swing.

Dropping the level by 10 and multiplying by 10 is probably going too far.  Factors of 1/2 and 2 maybe to save a particular circuit with available JFETs.

FYI, your R9 is very low.

[antonis]

and Welcome, of course..

[merlinb]

The other explanation I can think of is that, when increasing the U1B feedback resistor x10, Q2's R-off needs to be 10 times bigger to provide the same level of attenuation

I suspect that is exactly what is happening. Simplest solution would be to go back to your original resistors values and make R4 smaller, say 10k. That will buy you 6dB more offness than you started with. If you add a similar resistor to the second stage you get another 6dB. You could of course play with these shunt resistor values, but the smaller you go, the worse the noise gets (making them both 4.7k would buy about 20dB better offness than you started with...)

Run your FET switching off 9V for maximum headroom. You might also buy some extra offness by switching the control signal more firmly to ground, I'm not sure about that.

but it also forces to use 1k for R8 which I guess is not ideal

You're already using 1k for R9, any reason for that?

Don't forget that you can also put the switching across the feedback resistors instead (which will flip the control logic). By itself this will probably give worse offness than your current scheme, but you could combine both approaches together if you do feel like going down the route of inverting the control signal.

[stonerbox]

Welcome!

If you are looking for a super aggressive (-70dB suppression) but low count component gate then check out the design I did in December last year. Developed it for a big voltage swing project (18v). Do take heed in the fact that I am an absolute numbnut. Feel free to improve what I present.

https://www.diystompboxes.com/smfforum/index.php?topic=128374.msg1237746#msg1237746

                                               2022 updated schematic

[jsoto]

Thanks everyone for taking the time to reply! I didn't expect so many responses! What an awesome community

The cathodes of the diodes that go to the gates should be pulled up to +9V, not +5V.  That might help a bit.

If you have high Vgs_off JFETs you can bump your Vref up.  That will buy some margin in the off_state and lose some margin in the on-state.  You can only do this in small doses as changing Vref too much will eat into your signal swing.

The problem with bumping up Vref is that the highest voltage I can use is 9V, so the TL072 (9V powered) only has about 1.5V to 7.5V swing. Also, I want the output to be at line level (about 3.5Vpp). So, in this particular configuration, Vref is limited to about 5.5-6V. But still, maybe that extra 1V makes a significant difference so I'll definitely give it a try.

Dropping the level by 10 and multiplying by 10 is probably going too far.  Factors of 1/2 and 2 maybe to save a particular circuit with available JFETs.

I was definitely too ambitious. merlinb's solution for scaling the signal by factors of 0.5 and 2 seems like a good compromise. The only downside is that I would have to buffer the Vref signal (due to those 10k connected to Vref), right?

You're already using 1k for R9, any reason for that?

I used 1k with the idea of being able to set the cutoff frequency (33Hz) of the HP output filter regardless of load impedance (1k in parallel with any line input load - typically 10 kΩ or more - will always be ~1k) but now that I think about it, it doesn't make much sense... I would be better off just setting the 33Hz filter on the first inverting op-amp and make R9 bigger, or even getting rid of R9.

Don't forget that you can also put the switching across the feedback resistors instead (which will flip the control logic). By itself this will probably give worse offness than your current scheme, but you could combine both approaches together if you do feel like going down the route of inverting the control signal.

I hadn't thought of that option, if at some point I consider inverting the signal I'll definitely keep it in mind, thanks for mentioning it!

If you are looking for a super aggressive (-70dB suppression) but low count component gate then check out the design I did in December last year. Developed it for a big voltage swing project (18v). Do take heed in the fact that I am an absolute numbnut. Feel free to improve what I present.

Interesting design, thanks for bringing it up! I'll definitely give it a try.

So... Lots of options! I'll do some more testing over the weekend and come back to let you know the results.

[PRR]

Gee, somewhere I saw an excellent essay on audio switching.

Handbook for Sound Engineers, Glen M. Ballou -- The Steve Dove chapters, section 25.9 Signal Switching and Routing

Also Small Signal Audio Design by some guy named Merlin Doug Self......

I'm not going to tell you which plagiarized snippet is who, because IMHO you need BOTH books.

[bluebunny]

> Also Small Signal Audio Design by some guy named Merlin......

Doug Self?  Cracking read.  Merlin's books aren't too shabby either.

[merlinb]

The only downside is that I would have to buffer the Vref signal (due to those 10k connected to Vref), right?

Probably unnecessary if C1 is big enough.

[jsoto]

Handbook for Sound Engineers, Glen M. Ballou -- The Steve Dove chapters, section 25.9 Signal Switching and Routing
Also Small Signal Audio Design by Doug Self......

Thank you very much for the recommendation, PRR. I've had a look at the tables of contents and they both seem very comprehensive, definitely the kind of books I need to have at hand. I don't know how I hadn't come across them until now!


Ok so I've done a few more tests, without much success...

I have tried scaling the signal by a factor of 1/2 as proposed by merlin. It seems to have no effect when scaled before Q2 and a slight improvement when scaled before Q1, but only if I connect the resistor (R4 in merlin's design) to ground before C3. If I connect it to 4.5V after C3 there is for some reason quite a lot of bleedtrhough. I must be doing something wrong, although I have checked the circuit several times...



Also, looking at merlin's design, I still don't understand why use 9V when Vref is 4.5V. I get that using 9V ensures that the JFETs are fully turned-on, but is there any reason to do this from an off-state point of view? Does it improve attenuation? I would prefer to keep the switch at 5V because I use that same on-off signal elsewhere in the circuit.

I've tried increasing Vref to 5.5-6V, but it doesn't seem to have any effect. I've also tried running the JFETs at 9V (adding coupling capacitors before and after each JFET stage) and that doesn't seem to improve attenuation either. I suspect I have reached the "breadboarding limits", and what I hear is not the JFETs bleedthrough but in reality capacitive noise between breadboard strips. Actually, it must be that, because if I simply remove the JFETs from the circuit there is still the same amount of signal going through. I guess at this point I have to either order a set of PCBs or simulate the circuits. Are simulation softwares reliable for this use case? I have no experience with spice and I guess falstad is not suitable for this kind of situation.

One last question. From an off-state attenuation point of view, how would a design with an LM13700 compare to a design like the one I first presented? Right now I don't have any LM13700 to test with and although in this particular case it doesn't make sense to use one, I see it used in professional designs (mostly drum synths) without any additional off-attenuation stage.

[Rob Strand]

Also, looking at merlin's design, I still don't understand why use 9V when Vref is 4.5V. I get that using 9V ensures that the JFETs are fully turned-on, but is there any reason to do this from an off-state point of view? Does it improve attenuation? I would prefer to keep the switch at 5V because I use that same on-off signal elsewhere in the circuit.

It's more of a precaution against distortion in the *on* condition.

Actually, it must be that, because if I simply remove the JFETs from the circuit there is still the same amount of signal going through.

That's exactly when you know you have bigger problems!   It can't be the JFETs.   If you pull Q2 the only signal that can make it to U1B pin 7 is a signal on Vref.

With the JFETs left out, increase C1 to 220uF.   Do you hear any change in the signal leakage?

What else are you feeding into Vref?   If you have low impedances feeding into VREF that can modulate Vref.  A larger C1 cap will help but maybe you need to redesign the circuit to have a separate VREF for the other parts of the circuit.
(Even the lowish value of R4 can modulate Vref.)

You could have other problems.   Perhaps you have bad connections on the grounds.   That allows signal to be imposed onto ground wires and it will appear as a real signal.

Other ways you can get signal leakage is if the volume pot wires pass by non-switcheds audio tracks (or wires.)

[jsoto]

With the JFETs left out, increase C1 to 220uF.   Do you hear any change in the signal leakage?
What else are you feeding into Vref?

I've tried increasing C1 to 220uF and signal leakage does not change... I have nothing else connected to Vref (the rest of the circuit uses a 2.5V Vref).

You could have other problems.   Perhaps you have bad connections on the grounds.   That allows signal to be imposed onto ground wires and it will appear as a real signal.

If pull the jumper wire that carries the signal from the oscillator to R3 (leaving everything else connected), the leakage disappears completely, so I guess it can't be bad connections on the grounds, right?

I have to say that the attenuation achieved by the first design I presented is not bad at all, I only (barely) hear the signal when I turn the gain up to the maximum on my audio interface. It's a Scarlett 2i2 with a gain range on the line input of 56dB, and taking into account how much I have to turn up the master volume to hear the bleedtrhough at a significant level I would say that the attenuation is at least 80dB. That is why I was thinking that at such low signal levels perhaps capacitive crosstalk between breadboard strips / jumper wires may be the limiting factor in achieving the best attenuation.

[m4268588]

Your first design has a serious flaw. Crosstalk (from Op-Amp output, etc) to gate further worsens leakage.

Fix like this.

[Dormammu]

Why are D1,D2 diodes drawn in the wrong polarity ?
Control voltage needs 9V.

[Rob Strand]

If pull the jumper wire that carries the signal from the oscillator to R3 (leaving everything else connected), the leakage disappears completely, so I guess it can't be bad connections on the grounds, right?

Not really because then there is no current flow from the signal generator to the circuit.   When the current follows it causes an I*R drop somewhere in the circuit and that's what you are hearing.   It's also possible to get capacitive coupling across the tracks (that's can sometimes be blocked by adding caps) but by pulling the generator you will kill that as well. Maybe try lifting R4, C3, R3 in that order. 

If you get some results, in order to analyse what is going on you need to look at when the signal feeds through, how far the signal makes in through R3 thorough R4, then what tracks are close to what other track.   I can't see the layout so I can't comment beyond those general ideas.

[m4268588]

sorry. my mistake. There is almost no profit to improve leakage. But it's a better practice not to make SW-1 open.
Is it intentional that transition times of fall and rise are different?

[merlinb]

Also, looking at merlin's design, I still don't understand why use 9V when Vref is 4.5V.

Since your JFETs are in a virtual earth then 4.5V will work, but if they were in voltage mode you would need the full 9V to keep the gate voltage above the signal swing voltage. I was talking out of habit, sorry.

[jsoto]

Why are D1,D2 diodes drawn in the wrong polarity ?

They look wrong, but actually that's how it's usually done. I've seen some forum discussions about whether adding a diode is useful or not, but the vast majority of commercial designs that use JFET audio switches (Boss and Ibañez pedals, for example) add them. There are quite a few posts on various forums explaining why (I'm not sure I understand the reason myself, so I'll spare you my bad explanation).

But it's a better practice not to make SW-1 open.

Definitely, but I want to use an SPST push button as SW1...

Is it intentional that transition times of fall and rise are different?

It is indeed intentional, I tried using smaller values for R5 but the fall felt too abrupt. 1M is the one that sounded best to me.

Not really because then there is no current flow from the signal generator to the circuit.   When the current follows it causes an I*R drop somewhere in the circuit and that's what you are hearing.

I hadn't thought of the I*R drop. Maybe it's dumb, but I tried disconnecting the signal generator from R3 and pulling the signal down to ground instead (through a 10k resistor), and the bleedthrough disappeared completely. If it was a grounding problem I would still hear the noise, right?

Maybe try lifting R4, C3, R3 in that order. 

I tried lifting R4 first and it seemed to reduce the noise a bit, but it also got a little harsher. Removing both C3 and R3 (in that order) decreased the amount bleedthrough quite a lot. Is this a good sign?

If you get some results, in order to analyse what is going on you need to look at when the signal feeds through, how far the signal makes in through R3 thorough R4, then what tracks are close to what other track.   I can't see the layout so I can't comment beyond those general ideas.

I'm not sure I understand the first part, how do I do it? The layout is not the best for minimising capacitive coupling, partly because the source and drain of the JFETs are on adjacent tracks (although I can't do anything about that, it's the way the package was designed) and because the attenuated tracks are wired parallel to the non-attenuated ones. I'll try to improve the wiring and see if it reduces the bleedtrhough.

[PRR]

Why are D1,D2 diodes drawn in the wrong polarity ?

The drawing is correct. The leakage of a general purpose diode is far higher than the gate current of a JFET.

[Dormammu]

Why are D1,D2 diodes drawn in the wrong polarity ?

The drawing is correct. The leakage of a general purpose diode is far higher than the gate current of a JFET.

Maybe I misunderstand the general purpose of this scheme ? What exactly should jfets do ?