Solid state input stage WIP

[Steben]

What do you guys think? (yes the other part is currently not open for publication  )
An input stage does 2 things in my view:

- correcting the input signal to preamp level.
    Input impedance must be high enough, but mega's and mega's of ohms are not a quest. In this case given the high emitter impedance the input impedance is somewhat around 300k.
    Given the much lower supply voltage level of a SS device, the needed max gain is not that high. Hitting the rails is not the target of an input stage.
    Here we have +/- 4.5x? This equivalent of around 75x in a tube amp.
    The buffer brings the impedance low so any passive tone control can function on lower values.

- if seen as typical, a gentle harmonic spectrum is wanted.
    A simple BJT stage with no decoupling at the emitter has some feedback. This feedback reduces the enormous harmonic content a BJT has.

[antonis]

What are V1 and Vref values..??

('cause I see a heavily bottomed BJT..)

P.S.
Without seeing the rest of the circuit, I'd propose a CFP with a little of gain..

[Steben]

What are V1 and Vref values..??

('cause I see a heavily bottomed BJT..)

P.S.
Without seeing the rest of the circuit, I'd propose a CFP with a little of gain..

Man, that's a very simple little relatively Hi input Z circuit!

Using LTSPice I came up with:
Vs = 15V
Rc1 : 1k -> 470
Rb1 : 3k9 -> 3k3
Rb2 : 8k2 -> 12k

According to simulations up to 2V input the stage has some soft clipping before hard. That's good for a guitar amps input IMHO.

[antonis]

Man, that's a very simple little relatively Hi input Z circuit!

With the addition of a 10μF (or so) bootstrap cap you could lower 470k bias resistor value by an order of magnitude, resulting into both higher input impedance and more "stiff" bias (voltage drop across bias resistor practically independent of Q1 h_FE..)

P.S.
I'm not sure if dubling Q1 working current (my making Rc1 470R) contributes to higher Q1 h_FE, hence higher Q1 Base reflected Emitter resistance but if it's OK with your simulation, let it be..

[Steben]

Some sim output ....
0.1 - 0.5 V is classic guitar range. Cyan and magenta are boosted input range.
Given the soft negative cycle a soft positive cycle input aka rangemaster would make some interesting stuff....

[antonis]

How about R4->1k..??

[Steben]

How about R4->1k..??

R4 in sim? 1k doesn't do much.
R5 in sim / R4 original at collector q1: 1k makes for serious clipping / cut off



I made a sim of the first schematic with Vref biased at 15k / 3k9 divider. Somewhat same gain but much cleaner until more symmetric hard clipping.
Much less interesting... But is the sim correct?

Back to CFP:
Bootstrapping made for more gain with bias resistor at 10k... One of the results is less thermal noise no? Which is a surplus for an input stage.

[antonis]

I was talking about R4 in sim..

But you're right, so let it as it is..

[Steben]

Latest version.
I added the diode because it seems to round off a bit the hard clipping with large inputs.
Cq1 / Bq2 sits at 14.4V, Cq2 at 9.3V. If I get this closer, the diode might soften the output even more.

[antonis]

Latest version.

I'd make R2 47k and bootstrap cap 10μF (negative leg towards  R3/R5/Q1E junction)..

P.S.
Thermal noise difference between 10k and 47k is marginally less than 1μV (-118.6dBu / -112dBu or -120.8dBV / -114dBV)
(for a Bandwidth of about 5kHz..)

[Steben]

Latest version.

I'd make R2 47k and bootstrap cap 10μF (negative leg towards  R3/R5/Q1E junction)..

P.S.
Thermal noise difference between 10k and 47k is marginally less than 1μV (-118.6dBu / -112dBu or -120.8dBV / -114dBV)
(for a Bandwidth of about 5kHz..)

47k is noted.
10µF seems the classic choice, yet I noticed 1µF only seems to have a marginal bump way below audible freqs. And 1µF is easy obtainable in film caps...
I like avoiding electrolytics...

[antonis]

10µF seems the classic choice

Indeed but "classic" comes out of the rule of thumb:
"Bootstrap capacitor value must be greater than 10/(f_o*R_B), where f_o is the lower frequency of interest and R_B is the value of bootstraped bias resistor"
(>> 12μF for 10k and >> 2.6μF for 47k)..

The above attends to effective bootstrapping due to bootstrap cap negligible impedance hence negligible voltage dividing effect between Emitter and bias resistor..

[Steben]

10µF seems the classic choice

Indeed but "classic" comes out of the rule of thumb:
"Bootstrap capacitor value must be greater than 10/(f_o*R_B), where f_o is the lower frequency of interest and R_B is the value of bootstraped bias resistor"
(>> 12μF for 10k and >> 2.6μF for 47k)..

The above attends to effective bootstrapping due to bootstrap cap negligible impedance hence negligible voltage dividing effect between Emitter and bias resistor..

Yes, I understand. Will look up some film cap values.