Boss FA-1 Rehash Circuit Dilemna (Dilemma) Need Help

[Rob Strand]

Seems to be something indicative, arising from the Power Pump, with its extra power rail -9.1V, as it gives that +7.1V at the signal output, which is getting close to what the supply reading drops down to under power load with the effect on. Something to ponder and contemplate.

It's very suspicious but I can't seem to see the issue or link.

Also,
- If all is well and as drawn on the schematic, regardless of voltages there should be no DC across R12.
- R12 has +7.1V across it and the -9V rail has -7.2V, different sign.  So maybe a fluke correlation.
- The circuit should bias all the opamps to +4.5V  for both supply voltage selections.  (Is that happening?)

Something to try:
- power off
- remove C10 and R12
- set switch to HV supply
- Use DMM resistance range and try to find a resistance path from the output/output side of R12 to *somewhere* else in the circuit.

[FYI: your post yesterday was only partially rendered, today it is fixed.]

[bluelagoon]

Hey Rob, you don't think what I mentioned earlier might have some bearing on the issue -

Just wondering if the DC on the output has to do with the 100nF Decoupling Caps coming off IC2-(C16) and IC3-(C22) at their + power pins to Ground.

When they receive the +18V and the -9V at their power pins, with the +4.5 VR, just thinking , wondering, is this an imbalance having those decoupling caps at ground?

??
Meanwhile, I will remove C10 and R12, and check for resistance like you suggested.
Cheers.

[Rob Strand]

Hey Rob, you don't think what I mentioned earlier might have some bearing on the issue -

Just wondering if the DC on the output has to do with the 100nF Decoupling Caps coming off IC2-(C16) and IC3-(C22) at their + power pins to Ground.

When they receive the +18V and the -9V at their power pins, with the +4.5 VR, just thinking , wondering, is this an imbalance having those decoupling caps at ground?

Highly unlikely.

Without any obscure problems an output circuit like C10 + R12 simply cannot produce DC at the output.  That could be said regardless of the circuit.

A possible caveat would be an oscillation issue.   If you have strong oscillations it might be possible that a negative voltage applied to the +ve side of C10 is clamped (due wrong polarity on C10) then when the oscillation swings positive you get a positive voltage on at the output.   It's a quite a wild theory.  The fact the unit seems to work at both voltages except for the DC offset seems more like DC problem than oscillation problem.

It's all well and good to speculate and put things on the "to look at" list.   However if you look and don't find anything then those speculations can get crossed off.

[bluelagoon]

Added some of the missing features that were not there in original schematic shown at post 1
* Selectable Electra Fuzz in series after FA-1
* Selectable Buffer /True Bypass
*VFE MCU Relay Bypass
* Corrected the P Jfet symbol



The only thing missing now from the complete circuit is the Baxandall treble and bass in/out selection switch, which is just another peripheral that does not pertain to the issue of the excessive DC on the output signal.

What I cannot understand is that when the Electra Fuzz is switched in to the circuit, this then eliminates any DC on the output, taking it virtually back to 0V almost from the +7.1 with FA-1 preamp only engaged.

Will keep looking.

[Rob Strand]

In your latest schematic diode D4 looks like it is around the wrong way.   It could inject DC through to the output.

[bluelagoon]

Nah, believe D4 is correct, that's the way the VFE circuit has it. It has always worked well enough that way round.

[duck_arse]

The only thing missing now from the complete circuit is the Baxandall treble and bass in/out selection switch, which is just another peripheral that does not pertain to the issue of the excessive DC on the output signal.

so, not the complete diagram. waving your hand over a section of such a complex board layout and saying there's no problem there won't get the thing fixed. show the whole diagram, with all the switching stuff, otherwise, we waste our time groping in the dark. like looking for the R33 connection to the relay.

Nah

?? I think you should compare your J175 polarity to the datasheet of same.

[bluelagoon]

Yeah it might seem so Duck, but i beg to differ, I do have a little sense of what is going on within the circuit, as much as I do really appreciate the assistance here, I still just figured that a simple in out section of the circuit where no power attachments differ from the circuit within that switching arrangement really were just a redundant part not contributing to the situation. I already went the extra yards and put in a whole lot more than had wanted. Figuring its enough to deal with and get it sorted.

Also I'm running out of room on that piece of paper to put any more circuit detail on.

Since you asked though, I might get onto it just to keep the decorum.

I know you make a fair point of contention, so will try and get something a little more complete together.

Its not so easy when there are 2 boards involved with overlapping double ups of referenced components on each board like a C4 on top board and a C4 bottom board etc.

Also not sure what you are getting at with the J175 needing a data sheet look at, is it something to do with the power limitations on that transistor?

Cheers

[duck_arse]

well, and I will sound like a dick this time, I did the comparison, datasheet to your drawn schematic, now it's your turn.

[bluelagoon]

Come on Duck, give us a hint, I came here for getting of wisdom, and understanding, what's not working right in my circuit, you just seem to be throwing out cryptic clues, please give me some idea what are you alluding to?

Seems something wrong with the capability of the P Jfet, but like I say I am no electrical engineer, if you could please explain what the issue there is, I would be grateful, and better learned for hearing it.

Me and data sheets don't get on too well

Cheers

[duck_arse]

your schematic shows n-channel. the datasheet show p-channel, as does the vfe.

thank you for your good-naturedness reply.

[bluelagoon]

Thanks Duck, Okay, I learnt something. I think it is still the right transistor in place for the circuit, I guess it was just the way Peter from VFE drew up his original schematic, seems he must have placed a N channel in there instead of the correct P Channel jfet.

Good pickup, eagle eye Duck.

Will change it when I get a chance.

Cheers.

[Rob Strand]

Nah, believe D4 is correct, that's the way the VFE circuit has it. It has always worked well enough that way round.

My bad.  I just realized the JFET is a P-channel.  So diode direction OK.  Haven't look further at ckt.

Before I (mis)noticed the diode I was going to say to wire your own C10 + R12 directly to the IC output, using wires not on the PCB.  Then,  check for the DC.  At least than means the DC can get to zero.

I'm still suspicious of the JFET when the signal swing on the drain is high.  I need to look at it more closely but I was thinking does adding 10k (or 100k) from C10 -ve terminal to ground change the DC level?  For the electra part the diodes might be helping hide the problem, also the lower signal swing on the output.



FYI the JFET switch is messing with the output waveform when the signal level is high.
Kind of undermines the whole idea of having high supply voltage!

Adding a resistor from the drain to ground helps.  A smaller resistor is better than a larger resistor.
Without the resistor the waveform can get quite distorted!
Can't improve the -ve swing limit set by the JFET.

The problem also shows a -ve DC offset *when a large signal is present*.   Yes -ve DC offset.  The DC level starts at 0V but sags down when the signal is present because the output cap charges up.

Here's some circuit variations and the resulting output waveform for +/-6.8V swing at the opamp output.

[bluelagoon]

That is interesting Rob about the DC offset and the distortion from the j175 with a high level signal. As that is the transistor of choice in all the VFE Pedals bypass circuit. Would there be a better choice more suitable to higher signal level P Jfet to consider in place of the j175?

And thanks for the simulation on that jfet. Do you consider then the 10k added at the drain of j175, is therefore the best option added in?

Have removed the C10 and R12 from the board and will check for the resistance to other components later today when I get opportunity

Do you think still worthwhile wiring off board C10 and R12 to see if any difference?

- The circuit should bias all the opamps to +4.5V  for both supply voltage selections.  (Is that happening?)

Yes, checked all op amps are biased same at +4.5V at both power selections +9V and +27

[Rob Strand]

That is interesting Rob about the DC offset and the distortion from the j175 with a high level signal. As that is the transistor of choice in all the VFE Pedals bypass circuit. Would there be a better choice more suitable to higher signal level P Jfet to consider in place of the j175?

And thanks for the simulation on that jfet. Do you consider then the 10k added at the drain of j175, is therefore the best option added in?

The 10k definitely won't hurt.  It will help the circuit as it is now.   As you can see the distortion at the output isn't great.

Higher VP (Vgs_off) JFETs will distort less but you need a VP around that of the J175 in order that the micro can turn off the JFET.   So you can't fix the problem easily by changing the JFET.

The root problem is when the JFET is on the gate is at 0V, whereas it would work much better if the anode of the diode was at a larger negative voltage, say -9V.   This is where things get a little annoying and messy since the problem 0V comes from the micro.   When the JFET is off you still need to the anode of the diode to get pulled up to +5V.    The micro only has 5V swing for the gate signal whereas we are aiming for 5V - (-9V) = 14V swing.   You would need to add a transistor switch between the micro and the diode to get more gate  swing.    Off the top of my head I can't see an easier way around the problem.

Doing that stops the JFET distorting the -ve swing at the output.   However it can cause other problems which then need addressing.   The 100k+100n RC network feeding the diode ensure noiseless switching.   If we change the voltage diode from 0V to -9V then when the JFET turns off it now takes longer to go from -9V to +5V than it did before going from 0V to +5V.   The slower turn-off might let a click through - needs a lot more thought and testing.  In order to fix the negative swing problem we have to do some juggling to deal with the timing problem.

Have removed the C10 and R12 from the board and will check for the resistance to other components later today when I get opportunity

It won't hurt to check.

Do you think still worthwhile wiring off board C10 and R12 to see if any difference?

You can try it to prove that it can work once and for all.   I'm now thinking something weird is going on around the JFET.   The DC connections there so it makes a lot more sense.  What about the JFET pinout?

After your conversation with duck I'm assuming the unit is actually built with the correct JFET and the +7.5V issue still stands.

- The circuit should bias all the opamps to +4.5V  for both supply voltage selections.  (Is that happening?)

Yes, checked all op amps are biased same at +4.5V at both power selections +9V and +27

OK, so everything seems to be working correctly except for the last section around the JFET/100k.

[Rob Strand]

Here's an example of the improved swing with the negative voltage on the diode anode.

To pass -8.2V undistorted we need the diode anode at -4.4V,  don't need to bias as far much as -9V although it will still work




You have more swing so you will need more negative gate bias!

[duck_arse]

Rob - what polarity are your simming J175's? I can't hardly see which way the arrow points in those diagrams.

[Rob Strand]

Rob - what polarity are your simming J175's? I can't hardly see which way the arrow points in those diagrams.

The symbol is P-channel and the model is P-channel.

I didn't realize how hard to read that symbol was on a small scale . I'm always zoomed in on the screen 

As a cross-check: A negative gate voltage to turn on the JFET makes sense for p-channel.

Just for the record: "SPICE identifies depletion-mode FETs (all JFETs, regardless of polarity) by a negative VTO".

[bluelagoon]

After your conversation with duck I'm assuming the unit is actually built with the correct JFET and the +7.5V issue still stands.

Yes definitely the correct spec P Jfet as per the VFE circuit on their MCU Bypass
They do sometimes  include charge pumps in some of the VFE pedals, he may well make component adaptions to suit that don't
get the distortion trouble through the j175.

OK, so everything seems to be working correctly except for the last section around the JFET/100k.

Yes that's about it, the main crux of issues is the excess voltage at output in 27 volt mode, which gets excessive clicking popping when switched in and out.
Will try with that 10k on the drain of the j175, as seems proven a better option with the higher output signal.
Still need to get on and do that test for resistance to other components at R12.

So much to do and so little time
Even the dishes wont do themselves.
Thanks for the ongoing support, always appreciated. Cheers

[bluelagoon]

Did a quick test from C10 and R12 with +27V power on, effect engaged, haven't tested much yet for resistance from that point.
The ones I did test first were C10, R12 to the +9V point on main board at pin 4 of the right side 4 pin header
The resistance there with +27V power selected was 0.000
Tested it in the 9V switch setting, and it tested between C10,R12 and +9V pin at over 6 Meg ohm.
So definitely something amiss there, could be that voltage select switch.
Will keep searching.