Biasing NPN transistors

[fryingpan]

I've always used JFETs for some reason in my designs. I've never used BJTs (since wherever I didn't use JFETs, I just used opamps). What are the best practices for NPN transistors used as "common emitter amplifiers" (with degeneration and voltage divider biasing)? It seems like biasing the collector at half the supply voltage does not actually yield the highest headroom (and I aim more at Vcc/2 + Vbe), and also I don't really seem to understand what are the best practices for setting Vb with the divider.

[fryingpan]

Like, here is my attempt at biasing a 2N2222 for moderate gain (approx. 4 times, in order to ensure that +/-1V peaks do not get clipped).
It seems fine to me?



Also, these are the voltages and currents:
Vc = 5.36V
Vb = 1.52V
Ve (of course) = 0.85V
Ib = 7.33uA
Ic = 1.52mA

[antonis]

[antonis]

It seems fine to me?

Fine, so far as input impedance is neglected..

[fryingpan]

It seems fine to me?

Fine, so far as input impedance is neglected..

I'm coming from a buffer. A JFET with a 3.9k source resistor. It should suffice?

[antonis]

I'm coming from a buffer. A JFET with a 3.9k source resistor. It should suffice?

Buffer's output impedance (1/g_m) should be OK but about 8k input impedance of your circuit should load (lightly) your JFET buffer..
(input signal clipping might occur in conjunction with Source bias level and signal amplitude..)

e.g.
for 4.5 Source bias, signal negative waveform of greater than 3Vp should be clipped due to 3k9/8k voltage divider..
(JFET Source can't go lower than about 1.5V..)

[antonis]

As for the CE amp, it should be good to know what it's called to drive..

edit:

I aim more at Vcc/2 + Vbe.

Dunno how it comes..

For an Emitter bypassed resistor (decoupled via capacitor), Collector should be biased at (V_CC + V_E) / 2..
For unbypassed one, Collector should be biased at (V_CC + V_E*) / 2, where V_E* =  V_E X (1 + R_E/R_C)..

The later might seem confusing but you have to account for the reduced V_C - V_E headroom due to Emitter elevated voltage level for positive inputs..
(in Emitter decoupled mode, Emitter bias stays "firm"..)

[fryingpan]

Now, I'm not on my computer, but the source follower before is taken from the following (I have since modified the values for a J201, but the idea is the same):

https://sound-au.com/articles/jfet-f7-3.gif

The CE amp is then feeding a 25K volume pot (could be 100K but I want to keep impedances small, especially because BJT-input opamps really want up to 10K incoming impedance) and a non-inverting opamp, biased at half-supply through a 100K resistor. I'm trying to keep impedances at a 1:10 ratio (output to input). Oh, there also are some LEDs shunted to ground to get rid of extreme peaks before the opamp.

[fryingpan]

Also, with an unbypassed emitter, I don't think it is beneficial much to get Ve equal to 1/5 to 1/3 Vcc...?

[antonis]

Also, with an unbypassed emitter, I don't think it is beneficial much to get Ve equal to 1/5 to 1/3 Vcc...?

It strongly depends on Collector/Emitter resistors ratio..
e.g. for a phase splitter (equal Collector & Emitter resistors), V_E should be 1/4 V_CC..

P.S.
All the above concern linear (almost) amplification without distortion..

[fryingpan]

So, in this specific case (linear amplification, moderate gain), I should aim for, say, Ve = 2V? Although I'm quite sure that this design would work fine anyway.

[Clint Eastwood]

I'm coming from a buffer. A JFET with a 3.9k source resistor. It should suffice?

Why not change your JFET buffer into a common source amplifier with a gain of four, and skip the bjt stage?

[antonis]

Just follow the steps described in reply#2 and the formula in reply#6..

Or proceed as you like to..
(your circuit is sufficiently good for signals of amplitude lower than 1V_peak..)

[antonis]

Why not change your JFET buffer into a common source amplifier with a gain of four, and skip the bjt stage?

IMHO, 'cause it shouldn't have any fun...

[fryingpan]

I'm coming from a buffer. A JFET with a 3.9k source resistor. It should suffice?

Why not change your JFET buffer into a common source amplifier with a gain of four, and skip the bjt stage?

Because JFETs that can take a high input do not usually have decent gain at 9V. A 2N5457 won't cut it, unless I go for a cascode topology for instance.

[Clint Eastwood]

How much gain do you want then? you mentioned a gain of four at the start of the post, that is no problem even with a 2n5457.

[fryingpan]

The thing is, I wanted to keep things "simple" sourcing wise. Through-hole JFETs already cost a bomb, and are in short supply. J201s can be readily found in SMD form factor, which is a pain but can be soldered anyway to an adaptor. Other JFETs aren't so easy to find, and many are fakes. BJTs, on the other hand, are cheap and easily bought.

[Clint Eastwood]

Got it. If, after all, you do feel you need an affordable through hole jfet, I can recommend the J113.

[R.G.]

Good chart Antonis!

@fryingpan: There are some tricks that can be played with the input impedance. The input impedance of a CE amp the impedance of the biasing network in parallel with the apparent impedance at the base. As Antonis' chart notes, the input impedance due to the biasing resistors is R1 || R2. The  input impedance of the base is the current gain times the transistor's internal Shockley resistance of 25mV divided by the emitter current plus the unbypassed portion of the emitter resistor. For this circuit, the Shockley resistance is only about 10 ohms, so not much help there, but the base input impedance is beta times that plus the emitter resistor. The example circuit seems to be using 207 for beta. So the base looks like 200*570 = 114k. Could be less or more, depending on the individual transistor. So your input impedance is primarily set by your bias network.

Sometimes it's OK to make the bias resistors R1 and R2 bigger. As the chart notes, Vth = Vcc * (R1 || R2) and this has to be Vbase + Ibase * (R1 || R2). For biasing, you only have to get the right amount of base current into the base.  If you make R1 and R2 bigger and adjust Vth upwards to account for the base current times Rth, the resistor part of the input impedance goes up. I haven't played with the numbers yet, but if you can stand making  Vth a volt higher, you could change R8 to 470K and R41 to 180K. This makes the base voltage 1.542V and the bias network impedance 130k. So the combined impedance is 114K || 130K, or 60.7K.

Another way to do this is to leave R8 at 47K, make R41 18k, and insert a 120K resistor between the junction of R8 and R41 and the base. This reproduces a very similar Vbase and a similar base current and other bias points, and allows you to use a capacitor to bypass the junction of R8 and R41 to ground, lowering the bias part of the noise.

[fryingpan]

Good chart Antonis!

@fryingpan: There are some tricks that can be played with the input impedance. The input impedance of a CE amp the impedance of the biasing network in parallel with the apparent impedance at the base. As Antonis' chart notes, the input impedance due to the biasing resistors is R1 || R2. The  input impedance of the base is the current gain times the transistor's internal Shockley resistance of 25mV divided by the emitter current plus the unbypassed portion of the emitter resistor. For this circuit, the Shockley resistance is only about 10 ohms, so not much help there, but the base input impedance is beta times that plus the emitter resistor. The example circuit seems to be using 207 for beta. So the base looks like 200*570 = 114k. Could be less or more, depending on the individual transistor. So your input impedance is primarily set by your bias network.

Sometimes it's OK to make the bias resistors R1 and R2 bigger. As the chart notes, Vth = Vcc * (R1 || R2) and this has to be Vbase + Ibase * (R1 || R2). For biasing, you only have to get the right amount of base current into the base.  If you make R1 and R2 bigger and adjust Vth upwards to account for the base current times Rth, the resistor part of the input impedance goes up. I haven't played with the numbers yet, but if you can stand making  Vth a volt higher, you could change R8 to 470K and R41 to 180K. This makes the base voltage 1.542V and the bias network impedance 130k. So the combined impedance is 114K || 130K, or 60.7K.

Another way to do this is to leave R8 at 47K, make R41 18k, and insert a 120K resistor between the junction of R8 and R41 and the base. This reproduces a very similar Vbase and a similar base current and other bias points, and allows you to use a capacitor to bypass the junction of R8 and R41 to ground, lowering the bias part of the noise.

OK, but what I don't understand is why should I do so? 60K is too low an impedance for connection to a guitar (and arguably lots of pedals too, although it matters a lot less), and 8K is marginal (it basically works out to exactly ten times the output impedance of the source follower) but OK. A 1V input signal equates to 0.92V out of the source follower unloaded (probably can be biased even better but I'd say it's fine enough) and 0.86 loaded. A higher impedance would reduce this but would also mean an order of magnitude higher noise. It's a guitar pedal, so nothing too sensitive, but the lower the better? (Of course, by going with just the JFET wired as a common source stage I'd do away with a whole stage and get even lower noise, but again, JFETs are a pain in the arse to source).

Also, I see tutorials (that say a lot and say nothing at all) talking about much higher base currents than what I seem to achieve (like up to 40uA), and my collector current is kinda lowish for a BJT? I see much higher currents quoted around for general purpose BJTs, even if used as amplifiers and not switches. So am I sort of misusing the device? I don't have a necessity to save on current, it would be a mains powered pedal (well, through a power supply).