Sub-osc with CD4013 chip issue

[ElectricDruid]

Yes, you can see on the part of page 6 of the schematic that you posted how the various signals (Ext/Noise, Pulse, and Ramp) are mixed with 68K resistors and 10K linear pots (A10K). Then they all go down that VCF-SI connection to the filter on page 9.

Yves' circuit uses 220K resistors and a 47K pot (probably to match levels a bit better - the 4013 puts out a full 15V signal) so it gets wired into the same spot as the others.

[snk]

Ok, so the synth got back in its wooden case, with the faceplate screwed, etc. So far so good... until I noticed and odd behavior :
- First, everything is fine, the -1 oct sounds great, the -2 oct sounds great, in tune, etc.
- Then, after a couple seconds of using it, both octaves get shifted + 1 oct (so -1 becomes not shifted, and -2 becomes -1 octave), and while the -2 sub-osc sounds good (even if "only" playing 1 octave below instead of 2), the "previously -1 subosc" sounds thin and nasal (just like if the pulse width got maxed).

I didn't notice that previously, either because :
1- it wasn't happening and boxing the synth along with the add-on circuit made it happen;
2- when the guts of the synth were out, I didn't play enough with it to hear the issue (but really I don't think so);
3- Once boxed, I spent more time with the synth, tweaking every parameters, and one combination of parameters made this happen (it would be odd, but that might be something to consider)


One thing I find surprising, is that it doesn't happen right at the beginning, just after powering the synth on, but it happens after roughly 10 seconds, and the scenario is 100% reproducible.
It's like something needs to "charge" (?) and starts acting weird after it's charged (?)...

I will obviously open the synth again to check what can be wrong, but if these symptoms could give anyone a clue about some directions to investigate, I think it might help me troubleshooting this

[Rob Strand]

One thing I find surprising, is that it doesn't happen right at the beginning, just after powering the synth on, but it happens after roughly 10 seconds, and the scenario is 100% reproducible.

Yes, there's got to be something in that.

To me it's still unclear where the squarewave input is connecting in the circuit.  If it's AC coupled the 10 seconds could be related to the coupling cap charging up via the transistor and shifting the point in the square-wave where the CMOS gate clocks.   That would fit the scenario you see.

You really need do a deeper analysis and look at the signals with an oscilloscope, especially those around the input transistor on the mod ckt.

Putting that aside, and assuming you are just getting clock glitches you could just try adding one of those RC networks between the /Q output and D input on the first 4013 gate.   If the trigger is getting stuffed up like I mentioned earlier it's not really the right solution, even if it works!

[duck_arse]

please post the circuit diagram as you have it now. sounds like a clock input going floaty, or else glitching input.

[PRR]

look at the signals with an oscilloscope

DC coupled. What rises like the tide?

[snk]

please post the circuit diagram as you have it now.

Here it is : https://www.swisstransfer.com/d/c7dde5eb-4197-41c8-90b5-77cc82ad2b57
(else, it can be found in the link posted above : https://www.synthxl.com/yamaha-cs-10/ )

And here, just the VCO schematic, exported as a JPEG (you can find it on the PDF linked above) :
https://www.swisstransfer.com/d/71329b27-8c89-4dea-9237-1ad2d03f3862

And this is the layout i used (it's not very clean, as it was still a "work in progress for personal use" : the two red lines going to a red circle were the links I added afterwards to link pins 4 & 6 together and to ground)

sounds like a clock input going floaty, or else glitching input.

I have run out of time today, hopefully I can reopen the synth tomorrow and work further on it. I wish I can fix it without too much issues

[Rob Strand]

Are your connecting the the SQ in input of your circuit to TP4 on the Yamaha schematic? ,or are you connecting it further ahead where the 10k+1k5+68k meet.   You should use TP4 as it is a clean full-swing signal.   The other point is low level and could even be corrupted by very small amounts of signal feeding back from the other outputs.

It would probably be a good idea to wire the ground of your circuit to the ground side of the 1k5 resistor - ie. a ground in the vicinity of IC8 (IC8a, pin 1, 2, 3).

[duck_arse]

please post the circuit diagram as you have it now. sounds like a clock input going floaty, or else glitching input.

no, not the whole thing, I was wanting to see what you thought the circuit for this thing you built was. there is some further strangeness I can see on your board, but without your circuit, I dunno what's supposed to be and what's not.

[snk]

no, not the whole thing, I was wanting to see what you thought the circuit for this thing you built was. there is some further strangeness I can see on your board, but without your circuit, I dunno what's supposed to be and what's not.

Oh, ok : I haven't drawn such a thing (and never attempted to draw a schematic  ) :
- I took the Yves Usson schematic, and drawn the veroboard layout.
- Then, I changed the transistor to common emitter (to fit modern CD4013);
- Then, I added the suggestions Electric Druid pointed me to from the MW thread (adding 1k and 100nF to stabilize the octave down);
- Then, I added the "pin 4 to pin 6 to ground" wires (because without it, it wasn't working at all). It isn't drawn on the veroboard layout (it was added afterwards), and I used resistor legs on my build.

I can try to draw a schematic, but it would be my first attempt (so expect even more errors than in my actual circuit, ah ah), and I will need some time to figure out how to draw such a thing 

[duck_arse]

well I'm'a wondering why you have IC pin 1, which is an output pin, connected to +15V in all the layouts you have shown. it looks like it is, anyway. and a proper working circuit would never connect an output pin to either supply or ground, would it?

I'm also wondering why we have all missed that to this point.

[duck_arse]

also, a circuit diagram please. then we can see if you are taking outputs from Q's and using the !Q outputs only for clocking the data pin. all this stuff seems to count when something isn't quite working.

[snk]

well I'm'a wondering why you have IC pin 1, which is an output pin, connected to +15V in all the layouts you have shown. it looks like it is, anyway. and a proper working circuit would never connect an output pin to either supply or ground, would it?

I'm also wondering why we have all missed that to this point.

You're absolutely right     
This is the original schematic, drawn by Yves Usson and taken from his website :

https://yusynth.net/gear/CS10_en.html

(I need to go back to work, but will go back to the troubleshooting board and drawing board later this evening)

Thank you again so much !

[snk]

I made a cut in the veroboard so that the +15V doesn't go to pin1 anymore. I had good expectations, but sadly it din't improve things.

Are your connecting the SQ input of your circuit to TP4 on the Yamaha schematic? or are you connecting it further ahead where the 10k+1k5+68k meet. You should use TP4 as it is a clean full-swing signal. The other point is low level and could even be corrupted by very small amounts of signal feeding back from the other outputs.

It's connected to IC8, pin1, so it's TP4, right?

It would probably be a good idea to wire the ground of your circuit to the ground side of the 1k5 resistor - ie. a ground in the vicinity of IC8 (IC8a, pin 1, 2, 3).

Thank you for the tip, Rob.

[snk]

Yes, I double-checked with a photo I took before wiring (and featuring a yellow dot where i soldered the input) and the schematic, and i wired the square input just after pin1.

[snk]

also, a circuit diagram please. then we can see if you are taking outputs from Q's and using the !Q outputs only for clocking the data pin. all this stuff seems to count when something isn't quite working.

Reading that again, and comparing the 4013 datasheet pinout to my layout, and it seems that i made a mistake : I may have mixed Q and !Q, as (if I read you correctly) the 220k resistor coming from Q and going to switch 1 should go to Q (pin1), not !Q (pin2).
(but if I read the original schematic, both Qs -pin1 & 13- are unused, so I think i blindly followed the schematic)

[snk]

we can see if you are taking outputs from Q's and using the !Q outputs only for clocking the data pin.

On the schematic, both Qs are unused.
Audio out is coming from !Qs (pins 2 & 12)

Would you suggest another kind of wiring?

[ElectricDruid]

I made a cut in the veroboard so that the +15V doesn't go to pin1 anymore. I had good expectations, but sadly it din't improve things.

It needs to go to pin 14 instead, otherwise there's no power to the chip. Previously it went through pin 1 to pin 14, which isn't right, but at least it finished up in the right place!

[snk]

Hello,
While trying to spot mistakes, I am trying to figure out the best way to wire the chip, while keeping in mind what Duck_arse wrote : "we can see if you are taking outputs from Q's and using the !Q outputs only for clocking the data pin."

- The Yves Usson schematic I used (because it is designed for the Yamaha CS10), doesn't use pins 1 & 13, so Q is not used. Therefore (or from what i'm assuming), it is using !Q for both clocking the data pin and outputting audio.

Then I have searched the web to see how other sub-osc designs used the same chip (CD4013) :

- On the DIY site from Parasit Studio, !Q is also used :
https://www.parasitstudio.se/building-blog/cmos-workshop-part-3-octave-down


- On the Electric Druid site  , his study of the venerable SH-101 shows that Q are used :
https://electricdruid.net/a-study-of-sub-oscillators/



Which would be the best way to do? keep the original design to stick to the original schematic (even if we found some flaws in it), or do things "by the book", and route the outputs from Q to the audio out (while keeping !Q for clocking)?
I guess Duck_Arse was implying that the latter would be better, but since english is not my native language, i'd like to be sure

[snk]

I made a cut in the veroboard so that the +15V doesn't go to pin1 anymore. I had good expectations, but sadly it din't improve things.

It needs to go to pin 14 instead, otherwise there's no power to the chip. Previously it went through pin 1 to pin 14, which isn't right, but at least it finished up in the right place!

Mega 

[duck_arse]

I made a cut in the veroboard so that the +15V doesn't go to pin1 anymore. I had good expectations, but sadly it din't improve things.

It needs to go to pin 14 instead, otherwise there's no power to the chip. Previously it went through pin 1 to pin 14, which isn't right, but at least it finished up in the right place!

Mega 

yes, this. I thought you would have seen. so, please tell us you have added the supply volts to the supply pin.

a circuit diagram. WE ALWAYS start with a circuit diagram, then we are all talking the same language. and you must draw the diagram correctly, with electric and not mechanical details. so all your IC pin names are included on the circuit diagram, along with the pin numbers. just drawing the diagram will stop dumb problems and answer some questions.



so you posted THIS, but said you had changed it around the transistor. and then someone posted this



it was YOU! and said that was the original. allright, but what is the circuit you are building? we get confused about things, because they don't all match up.

see - the two transistor circuit takes a signal, inverts and inverts it in the schmitt [Rob et al - please correct me on that]. your original also doesn't invert the signal, but your modded version with collector connection will invert.

alright. the flip flop clocks [does work, changes state] on the positive going edge. then Q and !Q go opposite states. !Q has to go to the data or it won't divide, but you can also use the !Q output as THE output. but the two transistor circuit doesn't, it uses the Q output.

ok. so a few things - your from the !Q is going to be opposite level of the original from the Q. it will clock the next stage different edge to the original [relative to the inputted signal], and the final output will also be opposite of the original. and loading a data line can sometimes play silly with cmos, depending what it connects to. so if !Q does the data and Q does the driving, the two don't mix/load/cross over/mess up.

now none of this might be making a jot of difference to the circuit, but your build isn't working, and we don't yet know why. we don't know if the circuit is correct for logic cause you haven't showed it to us yet. and we don't know if the build is wired right yet, cause THAT follows from the circuit.

it all follows from the circuit diagram. any form - pencil on paper is fine - but the circuit as you intend to build it. please.