Rectifying an unbalanced signal

[fryingpan]

What matters more, on the other hand, is that reducing resistance linearly in the emitter's bypass branch of an amplifier basically produces an exponential envelope for the gain reduction, whereas a logarithmic response would be more appropriate (and for that to happen, the resistance variation must follow a reverse log curve). I suppose I could convert the control signal to the FET into something else. IIRC, a FET controlled linearly produces a logarithmic response.

[ElectricDruid]

What matters more, on the other hand, is that reducing resistance linearly in the emitter's bypass branch of an amplifier basically produces an exponential envelope for the gain reduction, whereas a logarithmic response would be more appropriate (and for that to happen, the resistance variation must follow a reverse log curve). I suppose I could convert the control signal to the FET into something else. IIRC, a FET controlled linearly produces a logarithmic response.

You're talking about the gain control part of this compressor circuit, right? I suppose that's why VCAs are popular for studio compressors, because they often have a log response.

[PRR]

exponential envelope for the gain reduction

In feedback configuration the gain-control linearity of the VCA doesn't matter a whole lot.

[ElectricDruid]

exponential envelope for the gain reduction

In feedback configuration the gain-control linearity of the VCA doesn't matter a whole lot.

The VCA response and envelope measurement would matter a lot for a feedforward design though, since there's nothing *except* those defining the response. THAT Corp have a ton of datasheets and app notes making a big deal out of (a) log response of the the VCAs, and (b) proper RMS measurement of the envelope amplitude. It's true though that I don't remember seeing any feed*back* designs, although perhaps I wasn't concentrating on that at the time...

[fryingpan]

Anyway, this is the way the Bearhug does things:




So, Q1 is an inverting amp, unity gain (-ish) when Q3 is off. The signal is taken from the MOSFET's drain and sent into another inverting amplifier, whose gain is determined by the comp pot (which should really be in a bypass branch to avoid a scratchy pot... although it's not directly in the signal path). Then the output of this amplifier goes into two antiparallel diodes... how is that a rectifier? When the signal is positive it just goes to ground. So it's just the negative portion that's being rectified (fine, it's a half-wave rectifier, but what's the point of the other diode?). And this is then filtered by the parallel of R8-R9 and C9 and that goes into the JFET (with a gate stopper? Why? And what's R6 for? The JFET is not really "biased" in any way).

[Rob Strand]

On the Bearhug, C8, D3, D4 and C9 form a voltage doubler.  I mentioned these earlier.  They use the signal from both polarities but they are not technically full-wave.  The positive cycle is "remembered" on C8 then both the positive and negative signal information is output on the negative cycle and stored on C9.   It's a quasi-peak detector here, like most compressors.   You can flip the diodes to get positive or negative output.

You can see figure 2, Greinarcher voltage doubler, (diodes flipped compared to Bearhug),
https://en.wikipedia.org/wiki/Voltage_doubler

[fryingpan]

On the Bearhug, C8, D3, D4 and C9 form a voltage doubler.  I mentioned these earlier.  They use the signal from both polarities but they are not technically full-wave.  The positive cycle is "remembered" on C8 then both the positive and negative signal information is output on the negative cycle and stored on C9.   It's a quasi-peak detector here, like most compressors.   You can flip the diodes to get positive or negative output.

You can see figure 2, Greinarcher voltage doubler, (diodes flipped compared to Bearhug),
https://en.wikipedia.org/wiki/Voltage_doubler

I still don't get how it works, as pictured. D4 is connected straight to ground, whatever goes through it might as well not be there. On the positive half of the wave, the signal goes through C8 and flows to ground, while on the negative half it has to flow through the resistor and capacitor (C9) which provide some inertia (the release). By what I see, attack is instantaneous.

[fryingpan]

Ok, maybe I understand now. On the capacitor's side, on the positive half, it charges up to V_gamma (and no more, because after that, there is no increase in voltage). When the signal shifts polarity, the other diode opens and charges C9 until it is fully charged, at which point the steady negative peak is reached. When D3 closes, the capacitor must discharge its negative voltage through R8 and R9 (if not bypassed), holding the negative peak. I get the peak detector part but I still don't get the voltage shifting part. Maybe it needs quite a few cycles of the input signal? But that means that the response of the compressor will be weird when first excited, and will then stabilise after a while?

[Rob Strand]

Ok, maybe I understand now. On the capacitor's side, on the positive half, it charges up to V_gamma (and no more, because after that, there is no increase in voltage). When the signal shifts polarity, the other diode opens and charges C9 until it is fully charged, at which point the steady negative peak is reached. When D3 closes, the capacitor must discharge its negative voltage through R8 and R9 (if not bypassed), holding the negative peak. I get the peak detector part but I still don't get the voltage shifting part. Maybe it needs quite a few cycles of the input signal? But that means that the response of the compressor will be weird when first excited, and will then stabilise after a while?

It's a bit tricky but once you see it you will get it.   Yes there is a delay.

Here's the main steps.  Drawn for positive case to keep it simple.  The Bearhug is a polarity flipped version of this.




Something else perhaps not so obvious is the DC bias voltage on the collector of the Bearhug transistor is completely ignored.  It appears as extra DC voltage on the first cap.  However, the output voltage and doubling process only cares about the AC signal.    A full wave rectifier doesn't so this as the DC bias will pass through.  So sometimes these doublers do a little more work for you.  For the case of the Bearhug is does even more, it creates a negative voltage for the JFET gate form a single positive supply.

For a compressor half-wave rectification and doublers do cause a delay in the output on one polarity.

[fryingpan]

Ok, maybe I understand now. On the capacitor's side, on the positive half, it charges up to V_gamma (and no more, because after that, there is no increase in voltage). When the signal shifts polarity, the other diode opens and charges C9 until it is fully charged, at which point the steady negative peak is reached. When D3 closes, the capacitor must discharge its negative voltage through R8 and R9 (if not bypassed), holding the negative peak. I get the peak detector part but I still don't get the voltage shifting part. Maybe it needs quite a few cycles of the input signal? But that means that the response of the compressor will be weird when first excited, and will then stabilise after a while?

It's a bit trick but once you see it you will get it.   Yes there is a delay.

Here's the main steps.  Drawn for positive case to keep it simple.  The Bearhug is a polarity flipped version of this.




Something else perhaps not so obvious is the DC bias voltage on the collector of the Bearhug transistor is completely ignored.  It appears as extra DC voltage on the first cap.  However, the output voltage and doubling process only cares about the AC signal.    A full wave rectifier doesn't so this as the DC bias will pass through.  So sometimes these doublers do a little more work for you.  For the case of the Bearhug is does even more, it creates a negative voltage for the JFET gate form a single positive supply.

For a compressor half-wave rectification and doublers do cause a delay in the output on one polarity.

So one could just use a full-wave rectifier and a P-channel JFET as the control element. It would be cleaner and easier? Also, P-channel JFETs are somewhat cheaper (as NOS of course). Also, I still don't get the purpose of the 1K resistor to the gate of the JFET and the 1M drain to gate resistor.

[Rob Strand]

So one could just use a full-wave rectifier and a P-channel JFET as the control element. It would be cleaner and easier? Also, P-channel JFETs are somewhat cheaper (as NOS of course).

It's definitely an option.

However, it's only simpler if the full-wave rectifier can be referenced to 0V.

If you need to add a DC bias to the opamps (eg. Vcc/2) then it's possible to connect a n-channel JFET to the VCC/2 point and have the full-wave rectifier go negative relative to Vcc/2.   Maybe hard to understand at first but circuit-wise not too bad.

Another angle is to use a very simple full-wave rectifier and remove the DC on the rectifier with coupling caps.   The JFET is biased independently of Vcc/2 in this example.
https://moosapotamus.net/2012/01/os-modified-orange-squeezer/

[Rob Strand]

Here's another way,





Note the transistor makes the compression curve harder.  More like dynacomps.  Purely "linear" rectifiers in a feedback compressors have a very low compression ratio.  The only thing that helps is the diode thresholds.

I suspect the rectifier should connect the opamp output with the DC bias present.




The reason I think that is the RC network on the inverter.

My suspicions are backed by this schematic,

[jorg777]

https://tinyurl.com/22qbt4gs

[fryingpan]

https://tinyurl.com/22qbt4gs

So, where's the catch? It looks almost too good to be true.

[fryingpan]

Like, I had imagined something similar could work. Bias the base at half supply and the collector or emitter of the second transistor will naturally "bump into" the other. Producing a rectified wave. You don't even need an emitter follower first technically. But there must be a catch, because otherwise others would have thought of it too (while most simple designs still take the trouble to rectify the two outputs separately and bias the transistor "correctly").

[jorg777]

Like, I had imagined something similar could work. Bias the base at half supply and the collector or emitter of the second transistor will naturally "bump into" the other. Producing a rectified wave. You don't even need an emitter follower first technically. But there must be a catch, because otherwise others would have thought of it too (while most simple designs still take the trouble to rectify the two outputs separately and bias the transistor "correctly").

You do want the PNP emitter follower, which not only provides the drive for positive half-cycles, but also cancels the Vbe drop of the output stage.

I didn't dream this one up; it's an old Moog circuit (possibly older than that).

[m4268588]

When the input signal level makes smaller.

[ElectricDruid]

So, where's the catch? It looks almost too good to be true.

That's what I thought when I saw the Crumar single-transistor version. They work, but they're a bit fussy. The levels need to be right, and the DC offset needs to be right. This version with the extra transistor might be a bit *less* fussy, but if there's a catch, that's it.

[fryingpan]

Like, I had imagined something similar could work. Bias the base at half supply and the collector or emitter of the second transistor will naturally "bump into" the other. Producing a rectified wave. You don't even need an emitter follower first technically. But there must be a catch, because otherwise others would have thought of it too (while most simple designs still take the trouble to rectify the two outputs separately and bias the transistor "correctly").

You do want the PNP emitter follower, which not only provides the drive for positive half-cycles, but also cancels the Vbe drop of the output stage.

I didn't dream this one up; it's an old Moog circuit (possibly older than that).

Oh noes, circuit no workey. 

Or rather, it does, but as m239485798645097826348791623498726349876 hinted (I'm sorry, can't be arsed to copy-paste the username ) it does attenuate the input signal a lot. So you still need to amplify it afterwards (not that it's much of an issue, it's a unipolar signal and you could amplify it to smithereens).

[jorg777]

So, where's the catch? It looks almost too good to be true.

That's what I thought when I saw the Crumar single-transistor version. They work, but they're a bit fussy. The levels need to be right, and the DC offset needs to be right. This version with the extra transistor might be a bit *less* fussy, but if there's a catch, that's it.

The extra transistor does make a big difference; at least in simulation I didn't do much tweaking at all.  Main thing is the load resistor of the first stage has to be pretty beefy because it is driving the collector and emitter of the output directly.

The circuit attenuates by a few percent, but unless it's used in test equipment, I don't see how that is very important.  You'll surely have something after this circuit (EQ, buffer, AC coupling, etc) and building a teeny bit of gain in should be pretty much free, if indeed you need a gain of exactly 1.