BBD chorus / Designing a Sample and Hold circuit (from scratch)

[Ksander]

Dear all,

I've been experimenting with a BBD and auxiliary circuitry (BL3208/BL3102/NE7555) to build a chorus effect. In principle, it works: I get clean, neatly-LFO-modulated clock signals and decent BBD output, which creates a chorus effect when combined with the input signal.

However, there is white noise. It is not clock noise - I can get clock noise by setting the base clock signal slow, but this disappears when the clock speed moves out of the audible domain. The remaining white noise seems like sampling artifacts. There is an old thread about tricks to deal with this, but these don't help sufficiently. Then there are these videos by Moritz Klein on BBD, https://youtu.be/4LjP5Y1yxXs?feature=shared where he uses a sample and hold circuit to get clean samples from the BBD output (see 29:36), which also makes the extensive filtering unnecessary. He also has a video on designing a sample and hold circuit: https://youtu.be/kIJqzkRe4do?feature=shared.

The videos are great, but they are for synths with bipolar supplies. I'm having trouble creating something for a 0-9v supply for my chorus circuit. Here's what I came up with:



The clock signal is filtered and fed through a transistor to get short pulses to trigger the S&H circuit. However, I'm not sure it works correctly/reliably. I only get output by omitting the 1M resistor/diode (as in Mortiz' circuits) altogether, or by having the diode the wrong way around.

I could use some advice to get this working well.

[Eb7+9]

this is an old idea, a way of avoiding the inter-clock glitches at the BBD output // which is what the output filter tries to "clean" away in typical BBD delay circuits that make use of more economical (linear) means ... the problem here is Moritz does it asynchronously using a ballpark time constant - which can only work in a somewhat limited (lower) range of clock frequencies; namely, at longer delay times ...

a number of years ago I came up with a high-speed synchronous version of this idea that does away with the limitations of an asynchronous solution // a fun design challenge in itself ... so, an alternate solution IS possible but it increases circuit complexity considerably - not to mention running logic at higher speeds than usual for common 40XX series CMOS IC's which is how I did it

moral of the story, you will run into a performance wall in the shorter delay range using an asynchronous approach - no way around it ... and if you try to drop the time constant using this approach the sampler will start suffering in other ways ... you need a scope to observe this hard constraint in action ... basically, the sampler starts bleeding thru the glitch artifacts it's trying to avoid once the clock rate overtakes the chosen time constant - manifesting as noise at the sampler output

[Ksander]

Thanks for the reply. I think Moritz demonstrates this issue also in his video. I'd be curious to see your solution, if you are willing to share? However, I don't think it has to do with whether(how) my design for the S/H part is flawed?

[diffeq]

one way to address the limitations of an asynchronous solution is to ditch the 3208 and use a microcontroller to create the clock and sample signals. then there's an issue with s/h, they have their own artifacts below certain clocking rate. then there's jfet channel resistance and other things making it imperfect - there are higher performance cmos switch topologies. I wonder if BBD's inner mosfets add some noise themselves.

by the time you solve all that, you are one step away from adding ADC+DAC and doing the delay digitally 

[Ksander]

one way to address the limitations of an asynchronous solution is to ditch the 3208 and use a microcontroller to create the clock and sample signals. then there's an issue with s/h, they have their own artifacts below certain clocking rate. then there's jfet channel resistance and other things making it imperfect - there are higher performance cmos switch topologies. I wonder if BBD's inner mosfets add some noise themselves.

by the time you solve all that, you are one step away from adding ADC+DAC and doing the delay digitally 

Well, you're right of course, and I actually went that way, using an Attiny85 and MCP ADC and DAC. This also worked, but was about equally noisy. Faster processors and more memory will probably work better, but I found that the programming and IDE become more difficult.

I'm just trying out things not too far outside my comfort zone.