Schematic of 0.5 msec Analog Delay for Through-Zero Flanging

[stm]

"When you promise you are in debt" thay taught me when I was a kid.  So here I present my work. I will organize this post in three sections:

* The actual schematic and curves
* Building hints
* Answers to the questions that have arised in this thread so far

So here we go...

-------------------------------------
1) Actual Schematic and Curves
-------------------------------------

Here is the schematic:



And here the performance curves as simulated with the nominal values indicated:




-------------------
2) Building hints:
-------------------

Due to the great bandwidth increase with the new implementation, I finally settled for 0.6 msec and 7 kHz bandwidth.

Notice a slight difference between resistors R11 and R27.  This is for maximum amplitude flatness.  If you use them both equal to either value, you will have a 0.4 dB dip or notch (depending on which value you use) around 5 kHz.

The 20 nF capacitor should be made of two 10 nF in parallel, so you just need to buy two different values only (of course it was impossible to have this capacitor 10 nF due to the high Q of this particular stage which demanded a minimum value higher than 16.3 nF to be realizable, so I settled for the next higher convenient value.)

Each row has a 4.5 dB of gain at every fourth opamp, instead of 26 dB of my former design (so total gain of the two sections is around 9 dB -- the value of 12 dB I posted before was wrong, now it is even better!).  As such, I don't think low noise opamps are needed anymore. A TL074 or similar JFET opamp would do fine.


----------------------------
3) Answers to Questions
----------------------------

The topology I'm finally using is "7th order 0.05º equiripple phase allpass".  I haven't found information on the internet about this so far. I had to go to a 20 year-old book to find the location of the poles for this design, and from that, getting the w's and Q's and then start building the stages.  Finally, I used a symbolic math program (Maple) to develop the 2nd order section transfer function and solve it imposing the restrictions of simple capacitor values and minimum insertion loss.

The frequency determining components are the two upper resistors of each 2nd order stage, and the lower resistor of the first order+gain stage.  Scale them accordingly and you will move frequency and total delay.

The 10k resistors and its neighbours settle insertion loss AND overall gain flatness, so you can't move them or you will destroy the amplitude response!  Unfortunately, there is no easy way to use a photocell or other controlled resistor to tune the filter. I've thought of that so many times, but tight component tolerance preclude doing something like that with this circuit.  I've been thinking for along time about how you could build a BBD-less flanger!


Well, that's all for now folks!

[puretube]

a certain Hendrik Bode was a master of all-passing and ladder-filtering in the first quarter of the last century...

[Vsat]

stm,
Amazing!! Any chance of making a parts kit plus PCB available?
Regards, Mike

[stm]

Yes, I am thinking to develop a kit with PCB for this if there is more interest.  I think an assembled and tested PCB would be in order, specially considering the large component diversity and their particular tolerance characteristics, and the hassle of debugging a circuit like this in case some component is mounted in the wrong location.

Just wanna try it with an actual flanger to see if the through-zero effect really shows up, and then post some samples.  This may take at least a week, though, 'cause currently I've got no flanger to test it.

Also, a flanger based on an MN3007 will be at the limit, since it requires a 1 MHz clock to get near 0.5 msec delay.  John Hollis's Ultra Flanger is supposed to do this.

For my own design I plan to use a shorter BBD like the MN3009 which I happen to have.  This unit will allow to get as low as 0.15 msec or so, which would go great with the 0.6 msec analog delay.

In the mean time, let me know if there is more interest in this idea so I further develop it.

[Ed Rembold]

I'm gonna breaboard this thing and see how it works "in real life", and see just how "fussy" it is, with standard value parts. I'll scope it, and report back.
(thanks stm)

Ed R.

[StephenGiles]

Steve Giles, if he is reading this thread, is probably thinking "Yes, yes, dear the Andes are very nice. Can we go home now? I have some, er "stuff" that needs doing."

Hey Mark, I would gladly have stayed in the Carribean or back in Equador. It took 2 minutes driving out of the airport car park yesterday morning to experience the poor, very aggressive driving in the UK. England is a very shitty country now, and you really notice it after being away for a couple of weeks. Give me Equadorian/Peruvian Indian people anytime - lovely gentle friendly folks, unlike the yob classes in Engerland!
Stephen

[stm]

I've been tinkering around with the idea of using standard components, so I converted the 1% resistor values to 5% (E24 series) and tweaked them for best performance.  The following table summarizes the recommended values.

R1/R17 3.0k
R2/R18 56k
R3/R19 3.6k
R4/R20 22k
R5/R21 3.0k
R6/R22 7.5k
R7/R23 150k
R8/R24 100k
R9/R25 62k
R10/R26 20k/22k (different values on each row)
R11/R27 24k
R12/R28 13k/15k (different values on each row)
R13/R69 62k
R14,15,16,30,31,32 100k

Also, I did a Montecarlo analysis on resistor and capacitor tolerance to see what the curves would look like when you use real components.  The following table summarizes the error in the amplitude response:

1) Res 1% tol, Cap 2% tol: Amplitude +0.75 / -1 dB
2) Res 1% tol, Cap 5% tol: Amplitude +1.5 / -2 dB
3) Res 5% tol, Cap 5% tol: Amplitude +2.5 / -3 dB
4) Res 5% tol, Cap 10% tol: Amplitude +4 / -4 dB

According to the above, for my personal use I would try to stick to 1% resistors and 2% capacitors, however 1% resistors and 5% capacitors are still reasonable.

The following graph illustrates the curves for 1% resistors and 2% capacitors:



And the following shows the curves for 5% resistors and 5% capacitors:



By the way, for those who don't know, the montecarlo analysis runs many simulations changing the actual component values with a value with an error in correspondence to the tolerance specified. This simulates how would your circuit behave in case you pick real components from a box and install them without measuring or selecting them. The idea to run many many simulations is to see the family of curves that show where your actual circuit response will lie, which is useful to determine if there is chance that it may violate some design restriction or specification.

There are different ways of picking toleranced components in a montecarlo analysis, which are: gaussian or normal distribution, uniform distribution, and worst case distribution. I chose gaussian distribution for these simulations, which is the most benign of the three. For instance, worst case will look all the cases where the components had maximum tolerance deviation, which is very unlikely to happen.  Just wanted to clarify this because if you run your own simulation you will find different results according what you choose.

Kind regards,

STM

[stm]

For some strange reason I'm getting corruption on the four pictures in this page (they're hosted on tinypic.com), and sometimes they even appear in the wrong place.  Just in case, here are the actual links (sometimes it is necessary to press RELOAD if it doesn't show up properly the first time):

Here is the 0.6 msec schematic with 1% resistors:

http://tinypic.com/5cqpg

And here the corresponding performance curves:

http://tinypic.com/5cqqt

And here the montecarlo simulation with R=1% tol and C=2% tol:

http://tinypic.com/5n2vd

And here the montecarlo simulation with R=5% tol and C=5% tol:

http://tinypic.com/5n2w5

Regards,

STM

[StephenGiles]

Thanks a million stm, I'll go for the accurate values first. I don't have any 1% resistors to hand so for now I'll spend a couple of hours measuring 5% types to get as near accurate values as possible using 2 for each one. Knowing me, I'll mess about with modulation when I get some time. I wonder though just how usable TZF is in a live situation because surely your sound level will reduce drastically when the flanging hits the thru zero point. In a studio though, it is a different matter of course, and would be very flash to use in a guitar shop!
Stephen

[Peter Snowberg]

Awesome thread STM!!!

[stm]

Thanks Peter, I've really enjoyed working on this!  Now's time to put it to the test...

[Vsat]

Steve,
Have your choice of  either summing or subtracting the fixed delay and variably-delayed signals. With summing, the two signals reinforce at the thru-zero point (and all  notches are gone).
Regards, Mike (busily soldering 1 percenters)

[puretube]

somebody mentioned "no feedbacking in a TZF" in this or the other thread

can`t remember whether it was on his site, in the H-C FX-forum, MusicToyz or here,
but Dave Fox mentioned s.th. about lots of experimenting and drawbacks
during R&D-ing his "Paradox" pedal, and how he was proud of having found a way, which signal to feedback where, to imply a "regen."-feature....

similar T-shirt here...

[stm]

Hi. Having analyzed the different topologies suitable for implementing Through Zero Flanging with a BBD + Analog Delay, I decided to post the possible schemes, since there is one option which is the most obvious but the least optimum. So here we go:



Regards,

STM

[StephenGiles]

Mike - I just got back from a play rehearsal for which my wife and I help out with some music. I used my stripboard ADA Flanger for the first time and I can safely say that it sounded great. I played an accoustic through a DI/Rat I made, plugged into a Behringer mixer. I connected the fx send to the ADA and the return into another channel of the mixer. It didn't like the low impedance output of the DI but behaved very well with the line level from the mixer. Hows the 1% resistors going? I can't face soldering anything yet, maybe in a couple of days when the jet lag has worn off!
Stephen

[Vsat]

Hi Steve (and list),
Good news...
Powered up stm's circuit last night (the 2nd latest version, since I had all the req'd values in 1% and 2% in the partsbox, built it on a PCB using a quick PCB layout, put a buffer stage at the network input). Tested it first with a sweep gen to make sure it was behaving properly. Then tried it with a flanger which gets down to 120 uS delay (network input connected to anti-aliasing filter output, network output connected to summing stage - the BBD does have a 12 KHz Butterworth which I didn't bypass). It does indeed give TZF sounds, somewhat different from my deltamod TZF unit, but still has the "kick" when you approach and go thru-zero. Tried both normal and inverse modes - have your choice of either cancellation (no signal) or reinforcement at the zero point. Works well with regen too - imparts a neat "hollowness" to the sound. Still preliminary.. took about 8 hours from start to first power-up yesterday.
Regards, Mike

[stm]

Some additional thoughts for getting a symmetrical TZF sound:

1) It is well known that for a "good" flanger sound a max to min delay ratio of 20 or better is required.

2) Also, it is believed that the clock frequency for the BBD should vary in proportion to the actual delay, meaning that the sweep remains more time at the low delay settings.

3) According to the above, one combination that would work is: fixed delay of 1 msec, min delay of 0.167 msec and max delay of 6 msec.  This has a max to min delay ratio of 36 times--quite good for flanging.  Also, the 1 msec fixed delay is at the geometric mean of the min and max delays, so if the sweep is done in this fashion the TZ effect will occur at the middle of the sweep and therefore will be symmetric.  The above could be achieved with a BBD like the SAD1024 and a suitable analog delay like the ones presented in this thread. However, the SAD1024 has two 512-stage delay lines, so in fact it can be used for both the fixed and variable delays!  I don't know why it hasn't been done before (or maybe I am not aware of this).

4) In order to get something usable for a MN3007 BBD, we will assume minimum delay achievable with this unit is 0.5 msec at 1 MHz clock.  So, lets design for 20 msec max delay, 0.5 msec min delay (40:1 ratio), and 3.16 msec fixed delay (the geometric mean).  In this case the fixed delay is too high for a reasonable implementation with an analog delay line.  A shorter BBD like the 256-stage MN3009 running at 40 kHz could do fine for this case.

5) I know the origin of this thread and the development of an all analog delay line was to avoid the usage of a second BBD unit.  I tend to be self critic, and even though I've worked a lot on the analog delay line, have to recognize that maybe it is still more convenient to use a second BBD for the task. To be honest, I'm not sure which is better, since both alternatives have their own costs, complexities and drawbacks.

Let me know what you think!  :wink:

STM

[puretube]

to be honest:
I admire your strive and labour - been thru similar experiments -
you got a great solution here!

For me: I`ll keep to the dual- (triple-/quad-) BBD solution
with proper layout and all precautions concerning
the known difficulties...

If there weren`t new reasonably priced BBDs on the market, I`d go Your way...

or: http://diystompboxes.com/sboxforum/viewtopic.php?t=25210

[Vsat]

Hey.... new ideas have to be tried!  Even if not always an optimal solution to the problem at hand, perhaps optimal for another use...

Currently I like the "karaoke" approach to TZF... easy to get very short delays...nice and quiet...
Regards, Mike

[Ed Rembold]

Mike,

When you say "karaoke" approach, do you mean, using a fixed digital delay for the "direct" signal?
Say it isn't so!

I very much like stm's original idea, I think it can be kicked up a notch (pun intended).

Ed R.