Schematic for Digitech PDS-8000 wanted...Maneco maybe?

[Gripp]

I made a more practical schematic, with names rewritten, and some enhancement like this. If someone is interested, I can post it.

Yes please!!!

You really seem to get the hang of this thing Basstyra. I've only got sort of a functional block view as to what it does.

Do you know what clock frequencies there are supposed to be for a given amount of delay time?
I mean, for the max in 8s mode, what frequency is the clock supposed to have to give exactly 8s of delay?
As I understand it you switch in different numbers of memory chips for the different ranges so once calibrated in one mode the others would be ok, no?
One should be able to calculate the clock frequency once knowing the memory structure, similar to a bbd based design if one knows how many stages there are and how the chip is configured, right?

Many questions but this thread has made me want to use my PDS a lot more

I have on and off the same sound as you have. I was able to trim it away but as I said, it seems to keep coming back. I changed for a fresh NE570 without any good luck. However, this was done without looking at the scope as I had a NE570 close by for another project. Will put the blue beast under the scope today!

[Maneco]

The delay time ranges is done by resseting the counters (4040's) at different points in their count...the memory chip is one,the 18 pin ,1mbit x 1
The clock for 8 seconds is around 16khz at the clock pin of the 4040,i'll check that in the scope...

[Gripp]

Aha!

Thanks man, another reply by the looping guru
Was it a good episode of prison break?

Is it resetting counters that does the trigger mode as well?
As I said, I would love to have it set basic delay time ( I guess by setting memory length) by trigger pulses and still be able to manipulate the sample clock, all this in normal delay mode.
I have had it like this somehow a few times.

Best!
Pelle

[Maneco]

You're welcome!

but better than prison break,is 24...can´t wait for the new season...

[Maneco]

I have the pds8000 board on my bench now,if you need some measurement,let me know

Good luck!

[Gripp]

For my part it's mostly about clock frequency values now.
And possibly if it would be possible to restart the memory readout by trigger pulses and still be in delay mode, enabling trigger synced delays but still have means to freeze them and manipulate sample clock.
Thanks again!

PS I do agree on 24, but think that the show has lost a bit of excitement over the last two seasons.

[Maneco]

I did some measurements in the scope today...the clock range at the input of the first 4040 is 1,6 uS to 7 uS,depending on the setting of the time pot

The bias voltage,with no signal applied to the input of the pedal should be 3,92 volts at pin 10 of the ne570...

Don´t know about the trigger thing,i suppose you have to mod it so the trigger input resets the counting,what normally happens in sample play mode,but the write pulses continue arriving to the ram chip,which is prevented to happen in this mode...as i told you,the schematic i have does not help

[Gripp]

That does the trick.
Thanks again!

[Maneco]

So,could you sync the delay to trigger pulses?

[Gripp]

No, not yet but I'm down in the schem and now it's perfectly calibrated with regards to ne bias and a good clock range with precise 4:1 sweep.
It was actually the first time I've seen an AD DA at work at the LM311 and TL022.
We'll see if the calibration drifts off again.

[Andre]

Could someone  please post a circuit diagram of this circuit, so the rest of us will know what you're talking about ?
This looks like an interesting circuit.

Thanks

André

[Maneco]

The lm311 works just as a comparator,the magic chip there is the mc14559,which "computes" the succesive aproximation for fast a/d convertion...the r2r network outputs the result for the other input of the lm311...when there's a match,the result is shifted into the dram chip...that's similar to the boss dd2 and dd3,except that those use a dedicated processor and are 12 bits...
And it would be cool if the redrawn schematic is posted....

[Gripp]

Got it. I had a hunch of what a sar did, now it's more clear.
It was just fascinating watching my input sine with all the sample pulses in it, knowing that it was fully digital just before. Only seen that at a BBD before.
Yep, that redraw would be great.

[Basstyra]

I'm sorry, I had much work to do this week... I didn't even slept from thursday to friday... 

So far, I didn't redraw the whole thing. I mostly replaced the name of the ICs and marked the pots.

http://basstyra.free.fr/temp/pds8000.jpg

[rove]

Hey y'all, just noticed this thread on the PDS 8000, one of my personal favorite delays.  I was wondering if anyone has gone in and replaced the switches on theirs, mine are very "touchy"
thanks!

[Maneco]

i did replace the switches...used two microswitches available at a local electronis shop,no problem...

[Basstyra]

I'm still on mine.

I replaced the NE570, same problem. The delayed sound is so compressed that the attack is way too violent.

I'm still working on the schematic, at the same time. Could someone help me there, what are your values for the trimpots (P1..4) ? I'm not 100% sure mine are correct... Thanks 

[Basstyra]

Nobody has a PDS 8000 at hand to check this ? 

[Gripp]

Sure!
Thanks a lot for the schem btw, been knee deep in my ADA clone lately so haven't focused on the PDS.

I think the trimpots name on my PCB don't exactly match the names in the schem however...
There's a miss in there somewhere.
My bias trimmer is marked P3 on my PCB (PCB is marked revC) and is 50k.
The feedback trimmer is P4 and 50k.
The clock trimmers are P1 and P2 and are 50k and 1M respectively.

[Maneco]

p1 50k
p2 1m
p3 50k
p4 50k

my board is revc