9v Sample and Hold

[soggybag]

I'm working on a sample and hold. I took a portion of the Maestro S&H and set it up to work with a 9v supply. I'm getting good noise and the LFO cycles properly. The problem is the LFO bleeds into the noise output into the sample and hold section.

(edit 0827, with changes suggested by gez)


When I use the audio probe I can hear a good amount of white noise at the source of the first FET. But there is a loud popping in sync with the LFO at that point.

Can anyone goive me any pointers on how to tame the LFO bleed through?

I built everything a breadboard and used 1458 dual op-amp. I notice the Maestro S&H uses 741 single op-amps. Maybe this helps keep the LFO signal sepparate from the noise?

[gez]

Try a a small cap on the FET's gate (10n or larger) plus a reverse bias diode (take a look at the bypass done in commercial effects units).  Also, try using a FET intended for switching (those are audio FETs if I recall).

PS  Any chance of you reducing the image by 50% and reposting it?  It's a tad large!  

[soggybag]

Thanks for the suggestions. I tried adding a cap on the gate of the first FET with no luck.

I suspect the noise is coming from LFO through the op-amp. I can hear the popping of the LFO at pin 1 where I suspect I should only hear noise. I also hear the LFO at pin 3! Which makes me think that the LFO section draws a lot of current at the peak of each cycle and this is the source of the problem.

I tried replacing the 47u cap on the voltage divider with a 1000u cap and this seemed to dampen the popping. I think there must be a better way of getting rid of the noise.

I don't quite understand how this type of LFO works. Can anyone explain it?

[gez]

I suspect the noise is coming from LFO through the op-amp. I can hear the popping of the LFO at pin 1 where I suspect I should only hear noise. I also hear the LFO at pin 3! Which makes me think that the LFO section draws a lot of current at the peak of each cycle and this is the source of the problem.

OK, didn't see that you were using a dual op-amp.   The two amps share common power connections so it's easy for spikes to be coupled through.  Try separate single amps (and use separate ground paths for each)?

[gez]

PS  Google relaxation oscillator for an explanation of how the LFO works.  The output slams from rail to rail (square wave) and during the transition current flows, which is what causes the spikes.  Using low power amps can help matters (ICL762X series for example).

Edit: didn't read this all the way through, but seems ok:

http://newton.phys.keele.ac.uk/ITTphys/RelaxationOscillator_ex.pdf

[Coriolis]

Hey, you do very nice drawings! Can't remember the last time I saw a handdrawn schematic that was actually readable...

C

[gez]

OK, also didn't see you were using a common divider for both halves of the amp (and everything else).  Bad idea!  Use a separate divider for the LFO.

[gez]

In the cold light of day a few thoughts come to mind.  

The LFO is set up as though you were using a dual supply.  When converting to single supply, using a divider and referencing everything to its centre often works in many circuits but the effect of loading etc doesn't make it as stable as actual ground (though using an op-amp for Vref can do).

The output from the LFO is fed back to the divider used as Vref for the whole circuit.  Bad news! C4, the 47u cap, will attenuate the squarewave signal the LFO generates, but it won't kill it completely, so you're now coupling this through to the audio chain as the filter is referenced to the same divider.  Using a larger value cap will attenuate the signal further but causes problems of its own (will take ages for the circuit to bias up and work as intended when powering up).

If you set the LFO up for single supply by giving it its own divider you should be able to get away with a common divider for the rest of the circuit (if you still get bleed-through follow my other 'advice'   ).  It would be more normal to see two 47k resistors for the LFOs divider, the centre of which connects directly to the +input of the op-amp.  A 24k resistor would then connect from the amp's output to the centre of this divider (these values should give the same performance).  Don't decouple the divider with a cap and don't reference anything else to its centre though!  The rest of the LFO circuit remains the same.

Attention to layout is critical.  Use separate ground paths for the audio and the LFO sections and join them at the -ve power connection.  Keep wires from the audio section well away from the LFO circuitry (or use screened cable).

[soggybag]

I made a change to the schematic (I posted it you may need to refresh). Everything makes sense except two things.

It sounds like the 24K will replace the 22K that is already there.

The .33 should also connect to the junction of the two 47K?

[soggybag]

Thanks for the help gez, I tried all of youur ideas but the LFO was still leaking into the the other signals.

I was also realizing that the gate of the first FET needs to be at 0v between pulses. The out put of the LFO in the orignal design seemed to be around Vr.

I decided to try a new approach and use a CMOS 555. Here's the new deisgn.


This seems to be working for the most part. I can measure a random voltage at the Drain of the second FET (CV). The range of voltages at CV need to be greater. I think I measured from 4.3 to 5V.

Got any suggestions or see any obvious blunders in this new design? I suspect there needs to be a resister to ground between the source of the first FET and the out of the op-amp.

I think I will need to increase the CV range to make it useful.

[gez]

The .33 should also connect to the junction of the two 47K?

No, it would connect to ground.  I didn't notice that you'd referenced it to the centre of the divider in your first schematic.  There'll be a slight change in LFO frequency now, but seeing as you've ditched this approach there's not much point recalculating values.

[gez]

I was also realizing that the gate of the first FET needs to be at 0v between pulses. The out put of the LFO in the orignal design seemed to be around Vr.

The output of the original should have swung from 'rail-to-rail', though in practise it would have been a volt or two short of this, so the 555 is a better solution seeing as you've reduced the supply to 9V.

I can measure a random voltage at the Drain of the second FET (CV). The range of voltages at CV need to be greater. I think I measured from 4.3 to 5V.

The drain needs to connect to V+ and the source to the source resistor to ground (you have them the other way around).  This probably won't make much difference as they're often interchangeable.  Try reducing the 100k resistor you have to the LED (not shown in this schematic).  Failing that, try sticking another large value resistor in series with R8 (the 1M resistor)?

PS  The 555 is drawn up wrongly.  Will post something soon.

[gez]

This should give the same duty cycle as the original:



Missed off the cap value, it's .33u (you might need to tweak its value anyway).

[soggybag]

Thanks for the help gez. I like your schem for the 7555. The on cycle though is too long. It's about equal with the off cycle. I like my version because the on cycle is very short.

I think the pulse that opens the first FET to sample the noise needs to be very short. I would like toget the on cycle even shorter if possible.

I'm still having trouble getting the output to be high enough. The best I seem to get is a range of about a 0.7V.

I could add another transistor or use an op-amp to amplify the signal at CV but this adds more parts. I keep thinking there must be a way to get a range of a 3v at CV...

[Eb7+9]

I think the pulse that opens the first FET to sample the noise needs to be very short. I would like toget the on cycle even shorter if possible.  I'm still having trouble getting the output to be high enough. The best I seem to get is a range of about a 0.7V.

...  you need a clock pulse that goes from rail to ground to make sure your first FET opens and closes properly/enough - the turn-on voltage of your FET can affect the input sampling range - try different devices with low turn-on specs ... the pulse width does need to be as narrow as possible of you want wide range  sampling from a white noise source ...

... for a narrow-pulse clock circuit you can use the standard triangle wave oscillator with a trimmer adjustable comparator following it ... it's ok  for this app ...

... but, check out Jennifer Elaan's variable-duty 555 circuit:

http://caladan.nanosoft.ca/diyclock.php

... also, page 344 in this data sheet (crowbar current) may be relevant to your noise question ...

http://www.williamson-labs.com/pdf/ICM7555C_1.pdf

~jc

[gez]

Variable duty cycle can also be done easily with the version of the 555 I posted.  The 555 is wired up like a Schmidt Trigger oscillator, so it's just a simple matter of a pot and 2 diodes to vary pulse width.

[Doug_H]

This thread might help:

http://www.diystompboxes.com/sboxforum/viewtopic.php?t=32834&highlight=sample

Doug

[soggybag]

Thanks for the tips. Like the look of the variable duty clock. I had been searching for something like this and the best I had found was the design in the last schem.

I had searched the Forum and read the post above before. I had been trying to keep the size and parts count to a minimum so the idea of using a 4066 or a bi-polar power supply was not appealing. That thread ran out with that last suggestion and did not seem to be resolved.

It seems that it should be possible to make a random voltage CV that runs off of 9V. From what I understand the key features would be:

Clock with a short sharp peak. The on or duty cycle would need to be short as possible with a peak of ? (I would guess 3 to 5V).

The gate of the first FET needs to be at 0V when the LFO is low. I noticed an interesting note on this schematic regarding FETs.
This example looks like it could be built with TL-082, leaving out the Input and trigger sections. But it runs on a bipolar supply so I think the LFO is low at Vr which would be above 0V on a singgle supply. So it has some of the same problems as my first design.

This last problem with the LFO is why I chose the 555 as an LFO. I'm not sure but I think the output should be go 0V to about 3V with each cycle. The LFO in my first example also introduced a spike in the rest of the circuit with each cycle which was also a problem I think a low power 555 would adress this problem.  

The LFO I had in the second design seemed to be short enough. The problem seemed to be at the first FET not holding the charge. Of course it was a little hard to tell what was going on there.

I had been trying to test by setting the LFO to a low speed and reading the voltage at CV with my Multimeter. At one point I was getting a pretty good random voltage between about 1 and 2V. But I changed a few things and wasn't able to get the same results again.

Can anyone recommend a better testing  method?

Of course I have no education in Electronics beyond a few Forrest Mims mini note books, feel free to tell me where my thinking is astray.

[soggybag]

After rereading this  http://www.diystompboxes.com/sboxforum/viewtopic.php?t=32834&highlight=sample  thread. I'll Quote PerryFrostwave:

"There is no reason why you can't have a 9v single sided noise generator and a single sided S&H. But since most of the old guitar S&H stuff has been lifted (I suspect) from analog synths (which are traditionally bipolar 15V supplies) we're stuck with it, unless we make new designs. (as we should Rolling Eyes ). "

The idea looks simple enough (famous last words i know). I think the key factors are getting the clock pulse correct to open the gate of the sampling FET to get a good sample. It seems this needs to be short and sharp. A low leakage cap to hold the sample would be a good idea also.

The FETs should have a high gate impedance. I was usign J201s but have since switched to 2n5457s as specced in "Ray's Single Chip Sample and Hold". I am going to try and build the Variable duty cycle 555 timer suggest Eb7+9 and try a few more tests.

[Joe Kramer]

When I use the audio probe I can hear a good amount of white noise at the source of the first FET. But there is a loud popping in sync with the LFO at that point.

Can anyone goive me any pointers on how to tame the LFO bleed through?

Hi!

In your non-555 design, you might try some fairly large power-supply decoupling caps on the op amps, and possibly the FET.  Start with something like 100-220uF electrolytics and put them as close as possible to the supply pins and the FET drain.  The LFO  might be causing a dip in current with each cycle, resulting in a pop.  Hope that helps.

Regards,
Joe