A Fantastic analog Flanger !!

[any]

Be Aware that the 100 series are a different circuit, I had one and it sounded quite different from my FL-01's..
Apparently, if you're looking for the schematic, look for the Korg one, it should be around... You can use the
Yamaha Partslist and have the same thing. Buying one is probably easier though...

Cheers,
Niels

I have a Yamaha FL100 flanger that's currently anti-working. Does anyone have a scheme for this one?
Thanks,
B.

[Auke Haarsma]

If anyone has a schematic (the links in this old thread are dead), could you please email it to me?
aukehaarsma at gmail dot com

much appreciated!

No one has the schematic to share?

[George Giblet]

This has the FL-01 and FLG-1 but not the FL100,

http://www.geocities.com/george_giblet/effects/Flanger_FL-01_FLG-1.png

(As I mentioned above: I doubt R34 is 100k it's more likely to be 1ohm.)

[1878]

My FL-01 arrived this morning and it's fantastic !! Only had a little play around with it but it's got that 'something' that instantly makes you go, 'Ooohh....'.

[Mark Hammer]

Would I be wrong in thinking that the diode series D7-9, plus the trimpot VR4 have something to do with tweaking the sweep  waveform in a more pleasing way?

[BDuguay]

Be Aware that the 100 series are a different circuit, I had one and it sounded quite different from my FL-01's..
Apparently, if you're looking for the schematic, look for the Korg one, it should be around... You can use the
Yamaha Partslist and have the same thing. Buying one is probably easier though...

Cheers,
Niels

I have a Yamaha FL100 flanger that's currently anti-working. Does anyone have a scheme for this one?
Thanks,
B.

Cool!
So, I should try searching for schematics of exactly which Korg flanger then?
Thanks again,
B

[skiraly017]

This has the FL-01 and FLG-1 but not the FL100,

http://www.geocities.com/george_giblet/effects/Flanger_FL-01_FLG-1.png

(As I mentioned above: I doubt R34 is 100k it's more likely to be 1ohm.)

Thanks!

[Auke Haarsma]

thanks indeed!

[any]

Cool!
So, I should try searching for schematics of exactly which Korg flanger then?
Thanks again,
B

http://www.geocities.com/george_giblet/effects/Flanger_FL-01_FLG-1.png

[Mark Hammer]

Looking at George's drawing, my attention is drawn to a few basic differences between the Yamaha and Korg versions of the circuit:

1) There is more bandwidth to the delayed signal in the Yamaha version.  Both C8 in the feedback path, and C16 in the MN3007 output path permit more low end to be processed.  Similarly, at the other end, both C6 and C9 in the feedback return point, shave off less top end in the Yamaha version.  The Yamaha may have a bit more lowpass filtering (a lower rolloff, actually) after the BBD. But not a humungous amount.

2) If you look at the mixing stage, you'll spot unequal mixing resistors (R11/R16) in the Korg version (68k/56k), and equal-value resistors in the Yamaha version.  My gut sense is that this is a reflection of the different approach to bandwidth between the two versions.  By allowing more bandwidth in the Yamaha version (especially low end, where more amplitude lives), the clean and delay signals are more closely matched already, and do not require offsetting mixing resistors to compensate.

3) The absolute weirdest part of this is the inclusion of R37 and R38 in the Yamaha version.  These two resistors, albeit low values, run counter to anything and everything that is common sense about that part of any BBD circuit.  Those two resistors limit the current from the clock output pins on the MN3101 clock generator going to the clock input pins on the MN3007.  This is conter-intuitive in a number of ways.  First, it is a common challenge across all BBDs that there is capacitance on the clock input pins of any BBD.  That capacitance is what sets the upper limit on how fast you can reliably clock the BBD.  It is the reason why you will rarely, if ever, see a single MN3101 or 3102 driving more than 2 BBDs, because the combined parallel capacitance of those multiple BBD clock input pins will serve to round off what OUGHT to be a nice crisp square wave arriving from the clock generator.  The other reason why this is weird in the current context is that, while analog delays prefer slower and less-challenging clock rates (so as to yield longer delay times), flangers prefer faster (and more challenging) clock rates.  So when other flanger designs with MN3xxx chips in them make a point of inserting a current-boosting buffer to feed the BBD a clock signal that can overcome the capacitance problem, why the deuce did Yamaha not only avoid a current buffer but also stick series resistors in the clock path to limit current drive?  My scalp hurts from the spot where I'm scratching my head over this one.  Are they somehow exploiting clock pulse rounding in some creative manner?

I'll explain the clock-rounding thng for the uninitiated, and why it is so critical.  There are two strings of FETs in a BBD chip.  You can see that the MN3007 has two output pins, pin 7 and 8.  Each of these pins provides the output of its own string of JFET "sample & hold" stages.  The clock sends the next sample from each path forward at the output in alternating fashion - now your turn, now your turn, now your turn again, etc. - and these two interpolated paths are combined.  When the clock pulse is nice and square, the handoff/switchover from sample A_n to sample B_n at the output is smooth and seamless.  It is as if there were only one high-speed sampling path instead of two parallel paths.  When the clock pulse is rounded, such that critical threshold for switching is not reached near-instantaneously, the outcome is akin to going: okay it's your turn.....nnnnnnnnnOW, and it's your turn.......nnnnnnnnnnOW.  And so on,  The non-contiguous switchover provides its own sort of sampling artifact that I'm not exactly sure how to describe, but it sure isn't natural or desired....according to theory.

Is there something about introducing such "handoff lag" via R37/R38 that ends up being a happy accident?  Never having knowingly heard either a Yamaha or Korg flanger, I can't say.  All I know is George indicated those resistors exist, and that I have never seen, in what has to be at least 50-60 different cases, anything in the clock path that would deliberately restrict current to the BBD clock input pins.  So, in my books, this is an anomaly that merits a full investigation and explanation.

[BDuguay]

Cool!
So, I should try searching for schematics of exactly which Korg flanger then?
Thanks again,
B

http://www.geocities.com/george_giblet/effects/Flanger_FL-01_FLG-1.png

Thanks!
But, didn't I read earlier in this thread that the Yamaha FL-01 and FL-100 are 2 different beasts?
B.

[oldschoolanalog]

3) The absolute weirdest part of this is the inclusion of R37 and R38 in the Yamaha version.  These two resistors, albeit low values, run counter to anything and everything that is common sense about that part of any BBD circuit.  Those two resistors limit the current from the clock output pins on the MN3101 clock generator going to the clock input pins on the MN3007.  This is counterintuitive in a number of ways.  First, it is a common challenge across all BBDs that there is capacitance on the clock input pins of any BBD.  That capacitance is what sets the upper limit on how fast you can reliably clock the BBD.  It is the reason why you will rarely, if ever, see a single MN3101 or 3102 driving more than 2 BBDs, because the combined parallel capacitance of those multiple BBD clock input pins will serve to round off what OUGHT to be a nice crisp square wave arriving from the clock generator.  The other reason why this is weird in the current context is that, while analog delays prefer slower and less-challenging clock rates (so as to yield longer delay times), flangers prefer faster (and more challenging) clock rates.  So when other flanger designs with MN3xxx chips in them make a point of inserting a current-boosting buffer to feed the BBD a clock signal that can overcome the capacitance problem, why the deuce did Yamaha not only avoid a current buffer but also stick series resistors in the clock path to limit current drive?  My scalp hurts from the spot where I'm scratching my head over this one.  Are they somehow exploiting clock pulse rounding in some creative manner?

Upon a quick review of the MN3101 datasheet:
http://www.synthdiy.com/files/2003/mn3101.pdf
On page 4 the manufacturer explains this. Check out  The "maximum clock frequency" notes and figure 3; the max clock frequency vs. load capacitance graph.
Now; as Mark said above; this would appear counter-intuitive. I totally agree. Especially for the high clock f's required for a flanger. And one with a 1024 stage BBD at that. I noticed this resistor thing a while back and have been "hair twisting' over it. However; it is the manufacturers datasheet so who knows? Could somebody please shed a bit of light on this?
Thanks!
Dave

[Mark Hammer]

Thanks for directing me to the datasheet (I have it, but looking at it is better, don't you think? ).

What you see from the diagram in the lower left on page 4 is something that I think many folks here already know, but never connected.  If you want to overclock your CPU to get higher frame rates in your favourite game, you need to dissipate the heat created, right?  Why?  Because when clocks run faster, they draw more current and produce more heat.  In addition to the "rounding off" thing I noted, the MN3101 datasheet indicates that when the clock frequency starts to move higher, more heat is generated, just like your CPU, and at a certain point that heat exceeds the power-dissipation capacity of the chip itself.  I don't know if that's the sort of thing that could be successfully handled by a simple heat-sink (and please, no water-cooled flangers! ), but the bottom line is that you simply don't want to exceed 200mw dissipation on a naked unadorned MN3101.

That same graph also shows that the greater the capacitive load the 3101 is attempting to drive, the more conservatively it has to clock.  So, you hit the critical 200mw threshold at a lower frequency when you drive the 4700pf of a pair of MN3005s, than when you drive a single MN3005 with some 2300pf capacitance on its clock input pins.

Now, the same figure also shows a hypothetical clock-freq-by-dissipation curve for a pair of MN3005s when there is 50R on each clock line.  If I understand the figure properly, that small series resistance permits a pair of MN3005s (8192 stages in total) to be clocked as high as 200khz, instead of the usual 100khz, before it hits the 200mw maximum.  Keep in mind that curve is only about power dissipation and is NOT about the integrity of the audio signal, as near as I can tell (and please correct me if I'm wrong).

So, extending the logic a little further, it would seem that Yamaha has plunked resistors in the clock path, conceivably in order to safely clock a little higher.  I still don't get how it works, but according to the table in the datasheet, it should.

Like my esteemed colleague oldschoolanalog, here, I am desperately in need of some explanation.

[flo]

> "I am desperately in need of some explanation"
After reading your post it seems to me that you already explained it quite well, thanks for that! 
Being able to state "the datasheet says so" is not to your satisfaction?

[Mark Hammer]

> "I am desperately in need of some explanation"
After reading your post it seems to me that you already explained it quite well, thanks for that! 
Being able to state "the datasheet says so" is not to your satisfaction?

No, not really.  I want to know why I have never seen similar resistors on any other flanger.

[George Giblet]

> I still don't get how it works, but according to the table in the datasheet, it should.

The whole message is hidden in figures 2 and 3 of the mn3101 data.  The why is actually easy to explain.

The clock is moddelled as a pulse train from 0V to Vdd.  The trick is to realize the clock output circuit can be modelled as an internal series resistance.    The added resistor appears in series with the internal series resistance.  The load can modelled as a capacitor to ground.

If you have a pulse train driving an RC network the power dissipated in the R (under circumstances where the R isn't too large) is largely independent of the R - despite the fact the R changes the waveshape.

When you add an external series resistance the same total power is dissipated however the power is now divided up into the on-chip part, and the off-chip external series resistance.  In otherwords the added resistance off-loads the power dissipation.

The MN3101 has an effective series resistance of about 100ohms so adding 50ohms drops the power on chip to (100/(100+50)) = 2/3, 2/3 of 200mW is 130mW.   This is roughly what the graph shows.

The power depends on the voltage so running at 9V instead of 15V greatly increases the maximum frequency (fig 3).

The degredation in the clock shape can also be estimated.  The rise time of the clock waveform is proportional to RC so by adding 50 ohms the rise time increases by a factor of (100+50)/100 = 1.5.   The rise time is fairly small like 1uS so the added resistor only makes that 1.5uS - not too bad.

[oldschoolanalog]

Thank you for that easy to grasp explanation George!
Now I can stop twisting my hair. 
All the Best,
Dave

[Mark Hammer]

So, does this imply that someone owning a BF-2 or similar "industry standard" flanger using the omnipresent MN3x07/MN310x pair could conceivably insert a pair of 51R resistors in the clock lines (and I assume this would involve cutting a pair of traces and adding some 1/8W resistors on the copper side) and drop the clock cap down from, say, 47pf to 33pf to get minimum delays approaching the through-zero point?

Here, I was thinking that moving beyond the 100khz ceiling necessitated use of current-driver stages and CMOS chips, when there may well be a simpler fix.

Or am I drawing unreasonable conclusions?

[StephenGiles]

Looks too simple to me

[George Giblet]

> Or am I drawing unreasonable conclusions?

I think so.  The added resistors help the *driver* drive higher capacitance loads.   It can't fix what is going on in the thing being driven, ie. the MN3007.   If you look at fig 3 of the MN3101 data sheet, at 9V the chip can drive the capacitance of the MN3007 to 1MHz or more.  What that says is the 51R resistors don't really have a place when driving the MN3007.

As far as driving the MN3007 at higher frequencies, the MN3007 is basically a set of MOSFETS.  The MOSFETs will have parasitic capacitive coupling between the clock inputs and the audio path, the coupling will increase as frequency increases.  Also the MOSFET will have turn on delays an that could cause an effective clock jitter between the MOSFETS, which could cause noise - is this significant? I don't know.  If you look at the mn3007 datasheet,

http://experimentalistsanonymous.com/diy/Datasheets/MN3007.pdf

there is a graph of noise level vs clock frequency.  The interesting thing is the noise increases with frequency but then it tends to flatten off at high frequencies.  The other interesting thing is some of the graphs show 200kHz and 300kHz limits.   There is no mention of power dissipation or heating in the data sheet.  I suspect that because this chip is driven and not the driver that heating is not an issue, unless the small losses in the many MOSFETs add-up.

One area where speed does have an impact is the transfer of charge from one stage to the next.  The MOSFETs have resistance and they must be on long-enough to transfer charge form one capacitor bucket to the next.  Extrapolating the insertion gain vs frequency graph in the mn3007 datasheet implies a significant drop on signal as the frequency is increased beyond 400kHz.  So perhaps that's the dominant mechanism.   From that perspective you would think the chip would be useable, at least to some degree, out to 1MHz.   This mechanism cannot be changed by playing around with clock resistors and the like, the mechanism is internal.

If you look at the MN3207 you see a much more radical drop at high frequencies.  There may be some trickery going on in the MN3007 to counteract the drop off and that may explain the positive slope of the insertion gain vs frequency graph at low frequencies.