3 or 4 octave up square wave ??

[gez]

When you say 'latency' Mark, do you mean that there's a delay before you hear anything at all, or is it just that the octave effect is delayed?

[markusw]

When you say 'latency' Mark, do you mean that there's a delay before you hear anything at all, or is it just that the octave effect is delayed?

It's just the octave effect is delayed. At the moment I'm testing the circuit with a software synth set up to give a square wave (i.e a stable wave). With the +ve input connected to the R8 feedback resistor there is actually no latency until the octave cuts in. With the +ve input connected there is some latency (actually it's too much) but once the octave is there the doubled square wave is definitely purer.

Regards,

Markus

[gez]

The only thing I can think of that might be causing this, and this is a guess, is that it takes a few cycles for C3 to charge to the average voltage output from the 1st comparator.  This would mean the integrators bias would take a while to settle back to half supply, hence the delay in triggering the following comparator.  Presumably the feedback in the original app note helps overcome this??

Have you tried directly coupling the integrator (minus any resistor in the feedback loop) and including ge diodes between its inputs?

Also, try it with your bass plugged in.

Other than that, I can't think of anything more really except to reconnect the feeback and put up with slight distortion of the output, though this might prevent you building up octave upon octave...

Perhaps save up for a POG? 

[markusw]

The only thing I can think of that might be causing this, and this is a guess, is that it takes a few cycles for C3 to charge to the average voltage output from the 1st comparator.  This would mean the integrators bias would take a while to settle back to half supply, hence the delay in triggering the following comparator.  Presumably the feedback in the original app note helps overcome this??

Thanks for your interpretation!

Have you tried directly coupling the integrator (minus any resistor in the feedback loop) and including ge diodes between its inputs?

Sorry, you mean with the +ve input connected to Vref  and C3 present?

EDIT: +ve input to Vref, but no C3 but with the two ge didodes? Yes, I tried. Didn't really work either.

Perhaps save up for a POG?

That's why I asked for the price of the HOG in the lounge (4 octaves up, yippie ). On the other hand, I'm not yet ready to give up on an analog design.

Regards,

Markus

[markusw]

Also, try it with your bass plugged in.

Will try next

One more observation. With the +ve input connected to Vref the latency only appears if I play a note on my synth with no input before. If I play a note and simply switch to another note then there is no latency!  (Latency btw is higher with higher notes). So might it be an idea to have an oscillator running at low level that is fed into the input of the doubler to keep it running. The amplitude of this internal oscillator had to be low enough to be overruled by the actual input signal. If now a gate is put after the whole doubling circuit only the input signal octave should be present at the output. Stupid??


Alternatively, is there an easy way to include a sample and hold circuit to somehow keep the doubler running while there is no input?? With a gate after the doubler this actually might work.

Markus

[gez]

Also, try it with your bass plugged in.

One more observation. With the +ve input connected to Vref the latency only appears if I play a note on my synth with no input before. If I play a note and simply switch to another note then there is no latency!  (Latency btw is higher with higher notes).

I think this is happening because of what I outlined above: the cap at the input of the integrator takes time to charge to the average output (half supply) of the comparator.  Once done, then following notes don't present a problem as the bias of the integrator is back where we want it (having drifted when the initial signal hammered it).  With a gap in playing, the cap charges/discharges back to its original state so they'll be a delay again with the next incoming signal.

I've thought of another way to bias things, but need to sketch it out just in case I'm missing something.  If it looks ok, I'll post an outline for the idea tonight.

[markusw]

Tried it again with bass. Actually, it's pretty much the same the same as with the software synth.

I've thought of another way to bias things, but need to sketch it out just in case I'm missing something.  If it looks ok, I'll post an outline for the idea tonight.

Cool  Thanks!

Markus

[gez]

I've sketched out a few things, but none will work.  The 'solutions' I came up with all require tri-state logic - either using a purpose designed chip or a modified comparator - and enabling the logic to act as a comparator when a signal is present requires a side-chain which, inevitably, is going to cause latency...in short, no fix.

Anyone got any ideas?

[markusw]

all require tri-state logic -

I've heard of the existance of this animal ...but what is it ?

either using a purpose designed chip or a modified comparator - and enabling the logic to act as a comparator when a signal is present requires a side-chain which, inevitably, is going to cause latency...in short, no fix.

Hm, sounds like doing it all (incl doublers) DSP would be a good choice Thanks for your effort anyway!

What about my ideas of running an internal oscillator or some kind of sample/hold circuit?? That stupid ?

Regards,

Markus

[gez]

Give me a while (I'm breadboarding this section to see if I can find a fix)...I like a challenge! 

[markusw]

Give me a while (I'm breadboarding this section to see if I can find a fix)..

I like a challenge!

Great! So wer'e at least two! 

Markus

[TELEFUNKON]

you`re not alone!

why integrate?

think of the 2opamp LFO`s:

1.) make a square out of the signal f;
2.) differentiate it, and cut off negative pulses;
3.) start a sawtooth (ramp) at each positive pulse;
4.) shift ramp above 0V DC-wise;
5.) add square and ramp (=saw 2f);
6.) put into comparator (=square 2f);

repeat at 3.) for doubling this again...

[gez]

OK, the problem is exactly as I described above.  Ideally, the comparator would need to sit at half supply when inactive in order to prevent the problem of 'latency' - It's actually the DC bias of the integrator being 'blasted' to one rail or the other by the initial input pulse and then gradually drifting back to centre base.

DC coupling with the back to back diodes between inputs does prevent the - input being pulled to one of the rails when the input comparator is idle, but it still creates a delay (long enough to be noticeable).

The only way to get a 'snap' reaction would be to replace that 10M resistor - incidentally, the Andy Flind bias method worked the best at biasing the integrator when AC coupled - with a 100k and directly connecting the input resistor to the output of the 1st comparator (no cap) though, as predicted, this creates distortion of the signal.  This would be fine for just one octave up, but no more I should think.  Anyway, if all you wanted is one octave you might as well build something simpler like Tim's circuit using an EXOR chip.

Tri-state logic would work, but is unnecessarily complicated for this circuit (yes, a PIC would probably be able to sort things out nicely, but talk about overkill!).  If you want to read up about it Mark, check out the CMOS Cookbook by Don Lancaster.  Basically it's a logic gate whose output is either high/low but the chip has an extra pin which 'disables' all the devices in the chip and their outputs then rest in the middle (half supply).

Mr Funk-On, I'd need to think about what you're proposing (hasn't clicked yet). 

[markusw]

you`re not alone!

1.) make a square out of the signal f;

low-pass filter -> comparator

2.) differentiate it, and cut off negative pulses;

differentiator -> will simply a diode in series with the signal be OK to cut off neg spikes?

3.) start a sawtooth (ramp) at each positive pulse;

4.) shift ramp above 0V DC-wise;

Hm, again how?   

5.) add square and ramp (=saw 2f);

non-inverting op-amp stage?


Although I believe I basically understood how it's supposed to work it will require a lot of reading 

Regards,

Markus

[TELEFUNKON]

GEZ got PM - please pass on to Mark!

[markusw]

OK, the problem is exactly as I described above.  Ideally, the comparator would need to sit at half supply when inactive in order to prevent the problem of 'latency' - It's actually the DC bias of the integrator being 'blasted' to one rail or the other by the initial input pulse and then gradually drifting back to centre base.

DC coupling with the back to back diodes between inputs does prevent the - input being pulled to one of the rails when the input comparator is idle, but it still creates a delay (long enough to be noticeable).

The only way to get a 'snap' reaction would be to replace that 10M resistor - incidentally, the Andy Flind bias method worked the best at biasing the integrator when AC coupled - with a 100k and directly connecting the input resistor to the output of the 1st comparator (no cap) though, as predicted, this creates distortion of the signal.

Thanks for checking!

IMHO, one conclusion is that the AN-41 is probably hard to beat in latency. Maybe with a little tweaking (e.g. slightly increasing C5) some compromise between doubled-square-wave symmetry and latency can be found.

What do you guys think?

If you want to read up about it Mark, check out the CMOS Cookbook by Don Lancaster.

Thanks for the hint!

2.) differentiate it,

Differentiation won't cause any biasing issues compared to integration, right? Are there any other potential problems ascociated with differentiation?

Regards,

Markus

[TELEFUNKON]

1.) Amplify hell out of it (maybe little lowpass before "neck pickup tone rolled down effect") like fuzzface-alike;

2.) through small cap; diode clamp after:

3.) see Schmitt-trigger/comparator-LFO (maybe use constant current to charge cap);

4.) op-amp adder (sig + DC);

5.) 2 resistors.

gives 50% duty cycle up!

cheerio.

[gez]

IMHO, one conclusion is that the AN-41 is probably hard to beat in latency. Maybe with a little tweaking (e.g. slightly increasing C5) some compromise between doubled-square-wave symmetry and latency can be found.

I don't think there's an easy fix for this circuit.  There are complicated fixes, but I prefer to keep things simple...so I'd be inclined to take a different approach if I were building such a circuit.

To date, I haven't built a single octave circuit, though I've experimented with many - my own designs and those of others.  They all have their quirks and I've never been 100% happy with any of them... and now that digital seems to be playing catch up (POG etc), I wonder if I ever will build one!

Well, there's still Mr Funk-On's approach to try (thank you kindly Sir)! 

[markusw]

Insert Quote
GEZ got PM - please pass on to Mark!

Thanks Mr Funk-on, also for your explanations re the differentiation approach! Will give it a try for sure (after some studies )

Regards,

Markus

[markusw]

Hi,

although the approach as outlined by Telefunkon is quite clear in theory (I even found some schems on sawtooth doubling) I have troubles how to feed the spikes generated by the differentiating cap/resistor combo into a sawtooth oscillator (derivative).

I suppose e.g. this one should be fine as a starting point

http://www.interq.or.jp/japan/se-inoue/e_ckt17.htm

Would be very happy if you could target me into the right direction!

Regards,

Markus