Stuff about CMOS based phasers

[George Giblet]

> but perhaps some of the distortion is slew rate related

The distortion is usually caused by the protection diodes.  The mainmechanism is outright clippers formed by the protection diodes at the CMOS gate outputs.  You can also get problems (depending on the device) where the control voltage dump into the audio path through the input diodes -the 4049 is a little better here.

To avoid distortion there's no option but to limit the signal level across the MOSFETs, since you cannot remove the diodes.  Look at the ETI and EhBadStone, there are dividers at the input to the bank of all pass filters to drop the level.  The penalty is higher noise contribution from the all-pass filters.

[puretube]

Brian, wanna know a secret?:
"everybody" builds phaseshifters around cascaded hipass filters = differentiators, nowadays.
because of the "ease" of having R_var to ground.   

[christian]

Apparently some posts were lost in this thread too
Anyway, I'd still like to know whats the peak-to-peak voltages on the badstone LFO?
Does it go from 0V to +1/2V as the "manual" pot?

To avoid distortion there's no option but to limit the signal level across the MOSFETs, since you cannot remove the diodes.  Look at the ETI and EhBadStone, there are dividers at the input to the bank of all pass filters to drop the level.  The penalty is higher noise contribution from the all-pass filters.

Nice hint, I didn't notice that divider!

ch.

[Mark Hammer]

> but perhaps some of the distortion is slew rate related

The distortion is usually caused by the protection diodes.  The main mechanism is outright clippers formed by the protection diodes at the CMOS gate outputs.  You can also get problems (depending on the device) where the control voltage dump into the audio path through the input diodes -the 4049 is a little better here.

To avoid distortion there's no option but to limit the signal level across the MOSFETs, since you cannot remove the diodes.  Look at the ETI and EhBadStone, there are dividers at the input to the bank of all pass filters to drop the level.  The penalty is higher noise contribution from the all-pass filters.

That may be true of specific invertor chips, and a worse problem with them because of that, but my sense is that Mike's distaste for the compensation network was more generally addressed to FETs, regardless of the form they come in, from MPF102 to tightly-matched 2N5952, to invertor chips. 

For those of you with the means, time, and generosity to do so, I'd be VERY curious to see scope images of audio waveform vs. input level, with and without a suitable compensation network, for "normal" FETs vs a typical invertor like a 4049 or 4009.

[bioroids]

For those of you with the means, time, and generosity to do so, I'd be VERY curious to see scope images of audio waveform vs. input level, with and without a suitable compensation network, for "normal" FETs vs a typical invertor like a 4049 or 4009.

I'm gonna do exactly that, as soon as my new soundcard arrives!

Miguel

[Vsat]

For some good info on using FETs for VC resistors, take a look at National Semiconductor AN-129 "A Linear Multiple Variable-Gain Amplifier" and the Siliconix appnote "Using FETs as Voltage-Controlled Resistors" and similar from Motorola etc.
The Siliconix appnote in particular has some very interesting graphs of small-signal resistance as a function of Vgs (showing the reason for the lopsided sound of FET phaser sweeps) and a comparison of distortion for the linearized and unlinearized VCR circuits. The National appnote has a useful comparison of distortion performance between "short-channel" and "long-channel" FETs. Some of these results can probably be extended to the MOSFETs used inside the CMOS inverter chips.... taking into consideration that the CD4049 etc MOSFETs are enhancement -mode rather than depletion-mode devices, whereas the JFETs are always depletion-mode. For FETs operated in the "resistive" "non-saturated" region, there is a nasty portion of the channel resistance vs Vgs curve where the signal handling is very poor and signal distortion peaks ...  the channel resistance is large here, as the FET is approaching pinchoff, and this corresponds to the "bottom portion of the sweep" in a phaser. At the other extreme, when the channel resistance is low, the signal handling can be quite good, in fact better than with OTAs... but the distortion peak near the bottom of the sweep defines the maximum signal level that can be applied... on the order of 10 mV p-p at the drain. One may choose to avoid this region altogether (limiting the sweep range) or use some means of improving the S/N while keeping the input signal small enough to avoid excessive distortion... such as a compander, low-noise circuitry or a linearizing technique.  Incidentally, in 4049 circuits, the MOSFET will be distorting like mad long before the on-chip protection diodes start to conduct.  Based on limited testing, discrete JFETs seem to have somewhat better signal handling and a more pleasant-sounding overdrive  than the 4049 (for comparison I built a "4049" out of 2SK30A-Y on a dip-header so it could be substituted in place of a 4049, with bias adjusted accordingly). The 2SK30A-Y was also used in an eight-stage phaser with the "series R-C" linearizing circuit, but with proper attention paid to low-noise circuitry better results were eventually had using the 4049, with the added benefits of excellent matching - no need for hand-selecting JFETs. The "series-RC" linearizer also has a disadvantage in that it provides a sluggish response to rapid control voltage changes - not good for S/H modulation etc. A modified version of the technique with additional components can solve this problem, one method is shown on the Hoshuyama website.
Mike

[bioroids]

Excellent information, I'm reading the Siliconix appnote now.

Do you know where I can find the National appnote? It seems I can't find it on Google and on National's site.

Thanks!

Miguel

[puretube]

http://www.diystompboxes.com/smfforum/index.php?topic=39904.0

[gez]

take a look at National Semiconductor AN-129 "A Linear Multiple Variable-Gain Amplifier"

Anyone have a link to this one?  Don't think I've seen it before.

The others have been posted before from what I remember:

http://users.ece.gatech.edu/~lanterma/sdiy/datasheets/transistors/vishay_fet_cvr_an.pdf

http://freespace.virgin.net/ljmayes.mal/comp/vcr.htm

[puretube]

you may have to pm MR COFFEE (see link in previous post)...

[gez]

Ah, if it's been posted before I'll have it on disc somewhere.  Thanks Ton.

[bioroids]

Thanks Puretube!

I was suscribing to receive the Linear Applications Handbook from National, until I found they are charging 30 U$. I know it is fair but I don't have the money at the moment (and I got to multiply that value by 3 here). Have anyone read this book, and is it worth the 30 bucks? I'm saving at the moment for R.G. layouts book.

Luck

Miguel

[TELEFUNKON]

isn`t it hidden here somewhere?

http://www.national.com/apnotes/
http://www.national.com/apnotes/apnotes_all_1.html

[TELEFUNKON]

found it slowly downloading but readible:
http://headfonz.rutgers.edu/FET-gain.pdf

thank you Mr. C., Pure, and Markphaser!

[George Giblet]

> nd a worse problem with them because of that, but my sense is that Mike's distaste for the compensation network was more generally addressed to FETs,

IIRC the diodes are the real problem.

When you drop the all-pass level with the divider the bonus is the signal level is small enough that you don't need the RC networks.

[Vsat]

The Siliconix appnote and others (plus Id vs Vds curves in FET datasheets) indicate that the FET VCR will only handle small signal levels in the resistive (ohmic/triode/unsaturated) region... 100 mV - 150 mV p-p max... and much less than this if the FET is being operated close to pinchoff.  The protection diodes will not turn on if a 150 mV p-p audio signal is AC-coupled to the drain.... the output protection diodes will require approx. +/- 0.6V signals to conduct. Something to watch out for,  when dealing with mV-level signals when using the VCR in combination with an op amp, is the possibility that the input bias current of the op amp flowing through the FET channel resistance could generate a significant offset voltage across the FET channel and increase audio signal distortion... a BIFET op amp would not have this problem, but the typical bipolar op amp with Ib of 50 nA-500 nA could have troubles when the FET is operated at high channel resistance.

The FET could handle larger signal levels if operated in the saturated (contant current/pentode) region, but the sweep range will be quite limited.... inspection of the typical characteristic curves shows that there is little variation in slope (small-signal resistance) with Vgs in the saturated region, compared to operation in the resistive region.
Mike