Orange Squeezer Trouble

[krister]

Hi,

I'm having a bit of problem with this OS build. I get sound but the bias pot doesn't seem to make any difference. The output is not very loud compared to other OS I made.

Here are my voltages:
Q1: G_.05, S_.5, D_9.3

Q2: G_0, S_.05, D_.05

IC: pin 1 _.49, 2 _5.49, 3_4.62, 4 _0, 5 .96, 6_1.42, 7_1.42, 8_9.35

Thanks for your help.

[krister]

I perf boarded this using RG's schematic.

http://www.geofex.com/

I can't seem to figure out why the voltages are so low on Q1 and Q2 compared to J.D.'s info.

http://www.generalguitargadgets.com/pdf/ggg_osq_instruct.pdf

Q1 & Q2 are J201

IC = TLO82

[krister]

When I pull Q2 out of the socket the full blast of the op-amp comes through. I have changed the transitors to two new J201's the signal is still attenuated with volume control all the way up. I have checked my connections, there is 0 volts at the gate of Q2 when power is applied. I am stumped at why this isn't working. There is no compression or effect change when the 10k trim pot is turned. This is driving me nuts. Does anyone have any ideas? Please help. Thanks.

Kris

[krister]

I can't seem to figure out how to insert a picture. Are there instructions on this site somewhere? Thanks.

[krister]

Here are some photos of the board work:





Ok, I figured it out, Thanks for your help.

Kris

[markymayhem]

So what was the problem?  How did you fix it?

[krister]

So what was the problem?  How did you fix it?

The problem is there isn't any compression, like the JFETs aren't doing their thing. The sound is very clean with volume full up, which means some signal is getting through, but not enough. The signal is being attenuated and that is it. There is no volume swell. Unfortunately, I haven't been able to fix it. The diode is a 1N34a the only resistor changes are 330k instead of the 390k and 2.2k instead of the 2.4k. I made an OS with a Si diode (same resistor changes) a while back and that fired up on the first try as expected and has worked well. I'm a bit baffled.

[R.G.]

OK, so let's take a look.

Pin 1 is much too low. I believe that something is wrong with the biasing of the opamp. Pulling Q2 out lets the signal come through, and the voltages look funny for the JFETs, so look for problems in the JFETs.

I believe that the gate of Q1 is shorted to ground, possibly through a reversed 4.7uF cap or a solder short.

Take a look at that and see what you find.

The J201 is not the best JFET for this application, as the Vgsoff is so small. But it should at least kinda work.

[krister]

OK, so let's take a look.

Pin 1 is much too low. I believe that something is wrong with the biasing of the opamp. Pulling Q2 out lets the signal come through, and the voltages look funny for the JFETs, so look for problems in the JFETs.

I believe that the gate of Q1 is shorted to ground, possibly through a reversed 4.7uF cap or a solder short.

Take a look at that and see what you find.

The J201 is not the best JFETs for this application, as the Vgsoff is so small. But it should at least kinda work.

What I put down as the voltage for Pin 1 was incorrect it should be pin 1 = 5.49v. The rest of the voltages are correct.

I used MPF102 JFET on my last OS, which worked. Should I switch to those instead of the J201's? Thank you for your input

[petemoore]

Pin 1 is much too low. I believe that something is wrong with the biasing of the opamp. Pulling Q2 out lets the signal come through, and the voltages look funny for the JFETs, so look for problems in the JFETs.
  Those OS Jfets are 'oddly wired', [not wired like a gain stage or buffer etc.] easily miswired, I don't know how to debug other than getting the board wiring to follow the schematic exactly.
I believe that the gate of Q1 is shorted to ground, possibly through a reversed 4.7uF cap or a solder short.
Take a look at that and see what you find.

The J201 is not the best JFET for this application, as the Vgsoff is so small. But it should at least kinda work.
  I would stick with the MPF102's.

[krister]

Pin 1 is much too low. I believe that something is wrong with the biasing of the opamp. Pulling Q2 out lets the signal come through, and the voltages look funny for the JFETs, so look for problems in the JFETs.
  Those OS Jfets are 'oddly wired', [not wired like a gain stage or buffer etc.] easily miswired, I don't know how to debug other than getting the board wiring to follow the schematic exactly.
I believe that the gate of Q1 is shorted to ground, possibly through a reversed 4.7uF cap or a solder short.
Take a look at that and see what you find.

The J201 is not the best JFET for this application, as the Vgsoff is so small. But it should at least kinda work.
  I would stick with the MPF102's.

I checked the 4.7uF cap it is in there the right way. It may just be the J201s not cutting the mustard. I'll let you know what happens. Thanks.

[petemoore]

Pin 1 is much too low. I believe that something is wrong with the biasing of the opamp.
  This would be a first debug task. or this:
  I believe that the gate of Q1 is shorted to ground, possibly through a reversed 4.7uF cap or a solder short.
  The J201's just might not provide the compression tone you like [might too though] iow the circuit should 'function' with J201's, maybe not for 'optimal' compression though.

[krister]

Switched MPF102s here are the voltages now:

Q1
G=.88v
S=2.91
D=9.05

Q2
G=0v
S=.88
D=.88

No compresssion yet  

[krister]

Pin 1 = 5.30v currently, is this too low? This is the output. Thanks.

[petemoore]

Pin 1 = 5.30v currently, is this too low? This is the output. Thanks.
  IIUIt correctly, the OS Opamp is a 'generic' gain stage, so if the output and _/+ inputs are all at around 1/2v bias, it's biased.
  Battery IIRC was like 9.32v, half of that wouuld be ~4.66v, pin 1 @ 5.30v is a little high..so pass on the grading of it to those who know whether this is acceptable, technically I believe bias should fall within +/_ 10%, this doesn't fall within that range, and limits the difference between idle bias and 9v [where the opamp runs out of voltage because...supply is 9v.], if it tries to swing toward 9v, you have the difference between 9v and 5.3v being 3.3v, so..[not subtracting opamp ineffeciency from that, whatever that is], there is 3.3v of workable swing room for the opamp to swing positive from idle bias, if bias point was exactly 1/2v [4.5v of 9v source], you'd have 4.5v worth of swing before the opamp ran into the V+ rail of 9v.
  What does the voltage divider read? [from ground, read resistance between the two equal value resistors strung across V+/V-.

[petemoore]

  ok ... this
  http://www.generalguitargadgets.com/pdf/ggg_osq_sc.pdf
  is much easier for me to read and...
  the divider is unequal, from ground to 470k > 390k to V+, that Would put the Vbias above 1/2v.
  And so I venture to guess the pin 1 voltage Is Correct.

[R.G.]

Pin 1 = 5.30v currently, is this too low?

No, it is now correct. The opamp is biased OK.

So the remaining problem is in the JFETs.
(1) Does the voltage on the gate of Q1 and the source and gate of Q2 change as you turn the 10K pot?
(2) have you checked your JFET pinouts? It is possible that Q2 is incorrectly inserted and is coducting from its "gate" through the 4.7K to ground.

[petemoore]

I get sound but the bias pot doesn't seem to make any difference. The output is not very loud compared to other OS I made.
  Many an OS bias pot do: 'nothing discernable', reporst also confirm very little difference otherwise.
    When I pull Q2 out of the socket the full blast of the op-amp comes through.
  There was a texted voltage change on pin1 ?
  IC: pin *1 _.49, 2 _5.49, 3_4.62, 4 _0, 5 .96, 6_1.42, 7_1.42, 8_9.35
  If pin 1 now reads 5.3, the rest of the voltages look pretty good, except the other side of the opamp is not used, and I would pin it to ground...something like hook the inputs to ground...anyway, that's neither here nor there...something to look into after the OA1 is settled in.
  When I pull Q2 out of the socket the full blast of the op-amp comes through....this lead *me to believe possibly the gain is set high with Jfet out, low with Jfet in...and that there is a wiring problem with the Jfet/gain setting circuit.
   I am stumped at why this isn't working.
   Could be something else, confirming the opamps bias, the only real thing left is the Jfet/variable gain section, which is the cause of many an OS trouble, I played heck deciding it was right and it still wasn't...
  As far as 'swell', the OS is 'yer basic, subtle and very nice compression', I'm pretty sure mine's 'right' and the compression it produces doesn't illicit much to call the 'swell'.
  I have checked my connections, there is 0 volts at the gate of Q2 when power is applied. Is this reading consistant/ or inconsistant with the reference voltages you found?

[krister]

I get sound but the bias pot doesn't seem to make any difference. The output is not very loud compared to other OS I made.
  Many an OS bias pot do: 'nothing discernable', reporst also confirm very little difference otherwise.
    When I pull Q2 out of the socket the full blast of the op-amp comes through.
  There was a texted voltage change on pin1 ?
  IC: pin *1 _.49, 2 _5.49, 3_4.62, 4 _0, 5 .96, 6_1.42, 7_1.42, 8_9.35
  If pin 1 now reads 5.3, the rest of the voltages look pretty good, except the other side of the opamp is not used, and I would pin it to ground...something like hook the inputs to ground...anyway, that's neither here nor there...something to look into after the OA1 is settled in.
  When I pull Q2 out of the socket the full blast of the op-amp comes through....this lead *me to believe possibly the gain is set high with Jfet out, low with Jfet in...and that there is a wiring problem with the Jfet/gain setting circuit.
   I am stumped at why this isn't working.
   Could be something else, confirming the opamps bias, the only real thing left is the Jfet/variable gain section, which is the cause of many an OS trouble, I played heck deciding it was right and it still wasn't...
  As far as 'swell', the OS is 'yer basic, subtle and very nice compression', I'm pretty sure mine's 'right' and the compression it produces doesn't illicit much to call the 'swell'.
  I have checked my connections, there is 0 volts at the gate of Q2 when power is applied. Is this reading consistant/ or inconsistant with the reference voltages you found?

The reference voltage was .6v at the gate of Q2, mine is 0v.

[petemoore]

  the 330k/390k sub just raisesthe Vbias up toward V+ a little bit, I would add a series resistance to that which brings it closer to 390k.
  The 2k4 for the 2k2 sub, at the Jfet section, isn't ahuge change, but it could well be that even a small value change here may make a big difference.
 
  The reference voltage was .6v at the gate of Q2, mine is 0v.
  .6v is 'off ground' 0v Is ground...
  I went through that Jfet section 10+ times at least, and miswired it at least twice...it looks simple, but can be a trickey wicket to get exactly right to schematic, which it has to be.