How close to match JFETs for phasers?

[sfr]

Okay, the neovibe got me into phasers.  Threw together a Phase 45 the other day.  used the Geofex JFET matcher and picked a couple of JFETs that had exactly the same Vgs out to three decimal places.  (I believe it was 1.696, but I'm not sure.)

Anyway, I'm looking at a pile of JFETs here that I've measured and labelled and contemplating building a Phase 90 - only thing is, I don't really know how close is "close enough" - I've got plenty of darn close pairs, like 1.696 and 1.697, but no quads that close.  Is two decimal places fine?  One? 

I've tried searching and while I'm finding plenty of posts about FET matching, and read what I can at Geofex.  (BTW, I was never able to find the full article at GEOFex by navigating the site, only the GIFs of the matcher; although Google turned up the FET matching article) And I guess now I understand better the whys and hows of it, but I guess I'm still missing something because I haven't really understood how to extrapolate from information exactly how close I need to match things. 

I guess I'll just socket and see, but any info folks would like to pass would be great!  Sorry if this is a dumb question.

[R.G.]

I don't really know how close is "close enough" - I've got plenty of darn close pairs, like 1.696 and 1.697, but no quads that close.  Is two decimal places fine?  One?

Not a dumb question. The short answer for me is - I don't know how close close enough is when measuring JFETs in that matcher.

The JFET matcher is not a definitive tester. It's more of an indicator. It's simple, just about free if you have a junk box, and gives really useful hints. But what it really can't do is prove that the Rdson of a JFET is the same to within X%, nor show that the phasing will be good to Y%.

What it does is make a huge improvement over easter-egging  random JFETs or not matching at all.

I have used JFETs which were off by a couple in the third digit ( e.g. 1.696 and 1.678) and been OK. What I did on my test batch was use a batch of 100, measure them all, then sort them by reading. This produced many pairs, a few obvous quads, and a couple of octals.

If it were me, I'd just go with the four closest ones. How close is that?

[Peter Snowberg]

If it were me, I'd just go with the four closest ones. How close is that?

Close enough for Rock & Roll.

[Mark Hammer]

My 2 cents worth is that it would depend on how crucial wide sweep is to your intended tone and use.  The value of matching FETs is that you don't have one or more FETs crap out on you and stop changing their drain-source resistance before you get to the end of the sweep.  Much like Olympic swimming, the "turnaround" at each extreme of the sweep has to be robust and smooth.  Having different numbers of stages participate at those "turnarounds" will not likely yield a satisfying tone, so you need to match them well if you want every stage to participate equally in the full sweep.  (For the uninitiated, it is not so much WHAT the FET's resistance is so much as that the resistance keeps changing in response to the LFO.  If the FETs are not well-matched, you can end up setting the gate bias-voltage such that *some* of the FETs keep changing their resistance in response to the LFO, but others say "Nope.  This is as far as I'm willing to change." before you get to the end of the sweep.  the result is what you might call a less intense phase-shift sound at the extremes of the sweep.)

On the other hand, if the intended use is a fairly modest sweep (and Uni-vibe type applications really only want a modest sweep), one might expect FET-matching to be less of an issue since it might be a trivial matter to find a gate bias voltage setting at which all FETs used are pretty much happy to vary their drain-source resistance a bit higher and lower than that.  Of course, if the intent is to have a "full service" phaser that will do both limited Uni-vibe sweeps, and then with a few toggle flips be forced into wide slow phaser sweeps, you need to plan around the worst (or rather most stringent) case scenario and aim for tighter matching.

Make sense?  Or have I completely misunderstood FETs?

[Thomas P.]

sorry to punch in at this one...

but wouldn't it then be better to use a mos inverter (e.g. 4007, etc)? As I see it the transistors on one chip should all be equal (and thermally coupled).....

regards,

[Seljer]

sorry to punch in at this one...

but wouldn't it then be better to use a mos inverter (e.g. 4007, etc)? As I see it the transistors on one chip should all be equal (and thermally coupled).....

regards,

I believe its the Electroharmonix Bad Stone that does just that

[R.G.]

It is, kind of. MOS transistors are variable resistors, just like JFETs, but enhancement instead of depletion mode.

However, I've not had all that much good luck with them as variable resistors for this kind of thing. And I suspect that if they were really good, we would see more CMOS inverters used for this in commercial products. I can't remember any except the EH that do this.

I think that perhaps there may be so much other junk around it on the chip that it doesn't work all that well.

Good place to experiment, but not a slam dunk for now.

[jimbeaux]

RA Penfold's "Electronic Projects for Guitar" has a Phase Shifter in it that uses the 4007UBE (I haven't built it though).

A couple of other projects in the book use these CMOS chips as voltage controlled resistors - (dynamic tremelo & auto-wah).

[petemoore]

  Just a notion/idea..
  Jfet comparator circuit.
  Get some 'close' Jfets going with the matcher, then figure out [if] a comparator circuit [could be designed]...to compare one Jfet to the other...?
  Use that to compare say 5 or 6 'close ones, getting two pairs that 'compare' nicely, then cross comparing a transistor from each of those two pairs...swapping them around until all the cross referencing looks like it's leaving you with the best matched transistors from your batch.
  Perhaps there is a way to measure their effective resistance changes in a live phaser circuit?...like set to a really slow sweep and using 4 DMM's and DMM *monitors? [people helping you synchroniously read the 4 dmms'].

[Mark Hammer]

Here's another idea from way out in left field.

In many instances/designs, the drain-source path is paralleled with a fixed resistor so as to set a maximum resistance and partly dictate the range of where the notches fall.  Ideally you hope the FET will keep changing resistance for the full extent of the sweep.  But what if instead the second parallel resistance was a second FET, such that if one FET crapped out 90% of the way through the sweep cycle the other would take over.  Maybe one of the FETs would be "stuck" at some max/min resistance and could not sweep any further but if the other one kept on-a-movin, then how much different would that be compared to a FET + fixed parallel resistor?

[R.G.]

I'll see your comparator and parallel resistor and raise you a microcontroller. 

It strikes me that most modern microcontrollers have a 10 bit A-D available and can be rigged to provide a DC output voltage. The slam-dunk solution to matching JFETs is to make up a test fixture up which feeds a nominal test signal into a divider made of a fixed precision resistor and a JFET set up as a variable resistor. The gate of the JFET is fed with a voltage from a D to A from the uC, which could be an eight bit PWM output, or could be a voltage from an eight bit digipot ($1.50 each). The signal read across the JFET is amplified and conditioned suitably to produce a voltage read by the 10 bit A-D.

So there is this Hammond 1590BB. Inside is a magic microcontroller, a few resistors and opamps, etc. There is a socket on the top of it, with a pushbutton and a couple of LEDs. There is a serial cable leading to a serial port on a computer - we all have computers, right?

So one LED is sitting there, glowing green. You insert a JFET, and press the bushbutton. The LED turns red for a second or two, and then turns green again. You remove and insert a new JFET.

The serial cable is feeding the measured data for 256 Vgs points back up to the main computer. The main computer just gets strings of data suitable for further processing.

The strings are of the form "Device number", "Rds at Vgs0", "Rds at VGS1"..."Rds at Vgs25". Presumably you can apply a sticky label with the device number to the JFET while it's being measured, so you can find matching devices later.

Having tested all the JFETs you like, you then take the device data, and you have a map of Rds versus Vgs at 256 points for each device. Plop into Excel and data-reduce.

You can pick out from this Vgsoff, Vth, range, Rdson, etc.

I figure cost of the tester as well under $75 even buying everything new. My workshop already has the PICs, the digipots, the Hammond boxes, probably all the resistors, LEDs, etc. I'd probably have to buy pushbuttons.

The accuracy does not have to be spectacular as long as the drift is low. Since matching is what's being tested, you get accurate results as long as the scale factors don't drift between devices.

[R.G.]

Come to think of it, roughly the same setup would test germaniums (roughly) and diodes for clipping voltage. hmmm...

[R.G.]

Hmmm...

PIC with 1kHz square wave output from internal timer. Drives dual digital pot, and reads A-D value, and reports test numbers through built-in serial port.

One section of digital pot plus fixed resistors divides 1kHz down to 100mV, under processor control for self calibration. Second section of digital pot makes control signal to gate of JFET through opamps for scaling.

Fixed 10K resistor and JFET D-S make resistor divider on the 100mV 1kHz square wave. Useful range is about 1K to 100K for JFET Rds.

AC signal from resistor/JFET divider fed to AC gain stage, precision rectifer, and integrator. Processor scales this to full A-D scale by diddling one section of digipot, above.

At power on, processor initializes, sets digipot to read full scale on DC signal by diddling calibration digipot. Waits for button press.

When button pressed, turns on "busy" LED;
sends device number on serial link;
sets control voltage to most negative;
waits for settling;
reads DC output;
converts to number;
spits number down serial cable.
increments control voltage to next most negative;
repeats with control voltage increment, measure, spit, until;
all 256 possible control voltgages done;
turns on "not busy" LED and waits for another button press.

Needs
PIC ($2.50)
Dual Digipot ($2.00)
three dual opamps
resistors
diodes
board
pushbutton
LEDs
box
serial connector
wire
solder
sockets if you're shy.

[sfr]

Wow. 

That sounds very cool and very interesting.  The more I hear about PIC stuff, the more interested I am.

Uhm, using the "simple way" - I ordered my JFETs in ascending value, from 1.288 to 1.813.  Figured the range between groups of four - looks like me closest 4 are within a .011 range.  (1.802, 1.804, 1.812, and 1.813)  I figure I'll use these, they should be plenty fine?

My largest range between 4 consecutive FETs is .175, but I can probably get two more sets within .05-.07 of each other, maybe even less.

[R.G.]

Wow. 

Sorry - I get carried away when I think up something.    I had to restrain myself from running out to the workshop and programming up some PICS. 

Figured the range between groups of four - looks like me closest 4 are within a .011 range.  (1.802, 1.804, 1.812, and 1.813)  I figure I'll use these, they should be plenty fine?

I would use those without a second thought. Put the two 1.80x ones on one stage and the two 1.81x ones in the second stage.

By the way, it is entirely possible that the third digit on the DMM display is questionable anyway.

You're good to go.