Understanding component value choices in JFET based pedals

[newbie builder]

I've been pouring over schematics of JFET based booster/overdrives recently in my latest attempts to stop painting by numbers and really understand what I'm actually doing, but I'm having a little trouble though understanding the decisions behind some different parts choices.

I have yet to encounter a circuit that does not have a decoupling cap near the output, but at the beginning of circuits I've seen different things. Sometimes I see a cap (.01 to .001 uf usually) and a 1M resistor to ground (which I understand is setting the intput impedance of the circuit to a large degree), but sometimes I also see in the beginning of the circuit, instead of a capacitor, what is labeled "R1" in the below drawing. What is the thought behind using a resistor vs. a capacitor in that place? What exactly is a resistor doing there? There may be a very obvious reason that I'm just unaware of, but I'm having trouble figuring out why somebody would use one vs. the other.

My other question is about the resistor labeled below as "R3," which I understand to be the negative feedback stabilizing resistor. As far as I can tell, its value is usually small (from 1k to 3k), and if I remember correctly the higher value resistor= more negative feedback in the circuit and less gain....is that correct? I also know though (through breadboard experimentations) that the value of this resistor can change very much how the transistor is biased, but I'm not sure why that is so. (I know that there are lots of threads about biasing on the forum, many of which I've tried to read through, but there are not as many threads that are about JFETs, but usually BJT transistors, so I'm not sure if everything applies in the same way to FETs)





These questions have probably been answered millions of times, but I couldn't come up with exactly what I was looking for answer wise in google searches or searches of this forum, so if anybody has links or words of wisdom they'd like to contribute, it'd be greatly appreciated.

Thanks-
Evan

p.s. I'd also like to thank Andrew Carrell for initially posting the blank template which I put values into. Andrew, if you would like me to re-draw the above schematic from scratch and take down the above image, I would be happy to. I just happened to find this and thought it would be much easier to just add in the values since I usually draw schematics by hand for myself and don't have a program/template that I normally use, but wanted to have a nicely drawn schematic to post to go along with my questions.

[R.G.]

I have yet to encounter a circuit that does not have a decoupling cap near the output, but at the beginning of circuits I've seen different things. Sometimes I see a cap (.01 to .001 uf usually) and a 1M resistor to ground (which I understand is setting the intput impedance of the circuit to a large degree), but sometimes I also see in the beginning of the circuit, instead of a capacitor, what is labeled "R1" in the below drawing. What is the thought behind using a resistor vs. a capacitor in that place? What exactly is a resistor doing there? There may be a very obvious reason that I'm just unaware of, but I'm having trouble figuring out why somebody would use one vs. the other.

You're making the very reasonable assumption that parts in like places do the same thing. That is almost but not always true.

First, what you're calling a decoupling cap (in this case C1) is actually a coupling cap. It's purpose is to couple (connect) the signal from the drain of the JFET to some other circuit, in this case the volume pot. A decoupling goes on the power supply connections between stages to prevent signal from sneaking through the power supply. The reason a capacitor is used for both places is that the voltage across a capacitor cannot change instantly - it takes power to make the voltage across it change. So the coupling use moves signal from one output to another input. The DEcoupling use shunts signal from the power supply to ground. Two different uses of the same characteristic of a capacitor.

A cap at an input or output is there to couple signal, but block the DC voltage levels inside the circuit from leaking out. A capacitor does this because its impedance (that is, how much it impedes electricity from moving) is infinite at DC, but decreases as frequency rises. So it will COUPLE signal at some frequency depending on the size of the resistors and cap, but block DC from flowing.

You have also picked a difficult example. There is an oddity about JFETs. They have the nearly-infinite input resistance of all FETs, but they also require a negative input voltage to bias them properly to amplify. In this circuit, the negative voltage is obtained by raising the source on top of the voltage developed through R3. The source is at some positive voltage, so tying the gate to ground through R2 makes the gate effectively more negative than the source. JFETs are the only common devices other than tubes that do this. Bipolar transistors and MOSFETs must have their control electrode - base or gate - raised higher than the emitter/source to make them conduct. So JFETs are hard. Professional analog designers often avoid JFETs because they're hard to work with.

With that out of the way, let's talk about R1. R1 is not necessary for the basic functioning of the circuit at all. It's there for secondary and non-obvious reasons. It is not there to couple signal into the gate. It's there to impede radio frequency stuff from getting to the gate, or possibly to lower the amount of input signal going to the gate. This last is unusual, but it does sometimes happen. The RF blocking is the most common use. Often you'll see R1 values of 100 ohms to 1K, and often there is a capacitor of 10pF to 100pF in parallel with R2. This forms a radio frequency filter to keep the circuit from picking up and detecting radio stations.

So you see circuits which have no input COUPLING capacitor when the circuits happen to need the same DC voltage as the incoming signal. This JFET circuit is one of those.

My other question is about the resistor labeled below as "R3," which I understand to be the negative feedback stabilizing resistor. As far as I can tell, its value is usually small (from 1k to 3k), and if I remember correctly the higher value resistor= more negative feedback in the circuit and less gain....is that correct? I also know though (through breadboard experimentations) that the value of this resistor can change very much how the transistor is biased, but I'm not sure why that is so. (I know that there are lots of threads about biasing on the forum, many of which I've tried to read through, but there are not as many threads that are about JFETs, but usually BJT transistors, so I'm not sure if everything applies in the same way to FETs)

Good intuition. Biasing for bipolars does NOT apply to FETs in general, and JFETs in particular.

Bipolars and MOSFETs are enhancement mode devices. That means that with no particular input, they don't conduct any electricity at all. You must enhance them by doing something to the control electrode to make current flow.

JFETs and tubes are depletion mode devices. With no particular control input, they conduct as heavily as they can. A JFET with the gate disconnected conducts its maximum current. You must do something to the control electrode to make them conduct less current or shut off.

An automobile is an example of an enhancement mode device. You must press on the accelerator to make it go. Imagine a depletion mode car. There would be a spring holding the throttle fully open all the time, and you would have to pull back on the accelerator to make it slow down or stop.

With that bit of info down, R3 does two things. First, for DC biasing, it creates the bias voltage that helps turn the device back down to  a stable condition. If we mentally think what happens when we first turn the power on, the JFET first conducts its maximum. The source and gate are both at ground, so a heavy current starts to flow. But as the current flows from drain to source, it causes a voltage to appear across R3. This voltage raises the source above the gate, which is tied to ground by R2. That reduces the current some, which lowers the voltage on R3. This settles down with just enough current flowing from the drain through the source to make the source high enough to make the gate lower enough to hold the current there. It's a simple self biasing setup. However, because JFETs vary a lot, the exact point where it will bias is very dependent on the exact device. Notice that the value of R3 and the innate current flow of the JFET (called Idss) is what sets the current through the drain. Vr1 has little to do with it.

The drain however lets the right amount of current through as called for by R3 and the gate-source voltage, so the current through it does not depend on Vr1. But the voltage across Vr1 and hence the voltage on the drain does. As you change Vr1 from 0 up to some larger value, the voltage across Vr1 rises as the resistance of Vr1 rises. That's because the drain current is set by what's happening at the source. So you can change the voltage at the drain by changing Vr1 without changing anything else.

The second thing R3 does is change the AC gain. Looking at the circuit and imagining C2 not there, the exact same current must flow through Vr1 and R3. If this is Id , then the AC voltage across Vr1 must be V = Id*Vr1 and across R3 is V = R3*Id. We know the source will follow the gate voltage closely because the R3 feedback forces it to, so the AC voltage at R3 must just be Vin.

So by some simple algebra, Id = Vin/R3, and substituting into the equation for the drain voltage, Vdrain = (Vin/R3)*Vr1, and
dividing by Vin we get Vdrain/Vin = Vr1/R3. That is, the voltage gain equals the drain resistance divided by the source resistance.

But back to C2. C2 is a cap, and we remember from the first couple of paragraphs that the impedance of a cap is lower as frequency rises. When the frequency gets high enough that C2s impedance is lower than R3, this starts increasing the gain again, because C2 shunts AC signal around R3. At some high frequency, C3 is effectively a short circuit, and the gain has risen to the value of the JFET's transconductance, gm times the value of Vr1.

Transconductance is the amount of current which flows in the drain for the amount of voltage change on the gate. It is a small signal parameter, which presupposes the JFET is biased at some stable DC setup. Then changing the gate voltage causes gm amperes per volt to flow in the drain. So if a JFET has a transconductance of 0.1 amperes per volt, and we change the gate voltage by 0.001V (one millivolt), then the drain current will change (0.1 A/V)*(0.001V) = 0.0001A or 100uA. That will change the voltage across Vr1 by Vr1 times the 100uA.Note that this can only happen when the source is shorted to ground by a capacitor at that frequency. Otherwise, the gain reduces to Vr1/R3.

I've blathered until I'm tired on JFETs. Did any of that help?

Need more? Need some point expanded on, or simplified?

Or just translated to English: I lapse too easily into Techese.

[newbie builder]

Let me start off by saying I can't thank you enough for your detailed and well thought out response- I'm definitely getting some of this stuff, and possibly the most exciting part for me about reading that post was that, thanks to your description of coupling caps, somethign just clicked in my brain and I finally get high-pass and low-pass filters (as well as coupling/decoupling caps and the use of a resistor to block RF). Before I knew how to make them and change the frequencies they were cutting, but didn't really know why they were doing what they were doing- now I actually understand what is going on, so thank you very much for that! All that being said, I've still got a few questions that I couldn't figure out the answers to yet.

With that bit of info down, R3 does two things. First, for DC biasing, it creates the bias voltage that helps turn the device back down to  a stable condition. The source and gate are both at ground, so a heavy current starts to flow. But as the current flows from drain to source, it causes a voltage to appear across R3. This voltage raises the source above the gate, which is tied to ground by R2. That reduces the current some, which lowers the voltage on R3. 

Why is the current is reduced when the voltage raises the source above the gate? I understand that it's getting raised above the gate, that makes sense to me, but I don't understand yet why that causes the current to reduce. It seems to me that if voltage is getting raised, since voltage is directly proportional to current, current would increase as voltage is increasing, so I must be missing something here.

C2 is effectively a short circuit, and the gain has risen to the value of the JFET's transconductance, gm times the value of Vr1.

Just to make sure I'm understanding these equations correctly, gm stands for the # that is the transcuductance of a given JFET?

Transconductance is the amount of current which flows in the drain for the amount of voltage change on the gate. Then changing the gate voltage causes gm amperes/volt to flow in the drain. So if a JFET has a transconductance of 0.1 amperes/volt, and we change the gate voltage by 0.001V (one millivolt), then the drain current will change (0.1 A/V)*(0.001V) = 0.0001A or 100uA. That will change the voltage across Vr1 by Vr1 times the 100uA.Note that this can only happen when the source is shorted to ground by a capacitor at that frequency. Otherwise, the gain reduces to Vr1/R3.

So, to pick an some values for VR1 and R3 so that I can see if I'm getting this, which I think I might actually be after having read this over many times, let's say VR1=10k and R3=2k7.
So that would mean that, if there was no C2, the circuit would have a gain of 3.7, but with C2 in place, and a JFET with a transconductance of .1 amps/volt, then with a 1mV change the drain current will change, 100ua (as you calculated above), which means the gain would be .001....which can't be right because the gain should be greater. So what am I calculating incorrectly at that point in time, or does the odd number I'm getting have something to do with the numbers that have been chosen being unrealistic.


Thanks,
Evan

[brett]

Hi
RG is a brilliant EE and communicator, isn't he?

Why is the current is reduced when the voltage raises the source above the gate? I understand that it's getting raised above the gate, that makes sense to me, but I don't understand yet why that causes the current to reduce. It seems to me that if voltage is getting raised, since voltage is directly proportional to current, current would increase as voltage is increasing, so I must be missing something here.

I *think* you might have missed the fact that it's the voltage across the resistor that's increasing, so the gate is looking more and more negative with respect to the source.  The same technique is used in tubes.  Raise the value of the source/cathode resistor to turn the device towards off.

So that would mean that, if there was no C2, the circuit would have a gain of 3.7, but with C2 in place, and a JFET with a transconductance of .1 amps/volt, then with a 1mV change the drain current will change, 100ua (as you calculated above), which means the gain would be .001....which can't be right because the gain should be greater.

The 3.7 is cool.  That's a common figure for such a circuit. 
However, the 100uA times a typical Rd of 10k is 1 volt (for 1mV input to the gate).  1 volt output per 1mV input is a voltage gain of 1000!  Seems a bit high to me, but we're talking ballpark figures here.  For transconductance of an MPF102, which is about 5mA/V, 1 mV input gives 5 uA x 10k = 50 mV output, or a gain of 50.  That's better.   

But I'm no expert, so check my assumptions and my math! 

JFETs are really nice devices with lots of great characteristics (high input resistance, nice distortion etc).  Have fun with them.

[db]

To understand source biasing it is worth having a look at a datasheet for a JFET like this:

http://www.fairchildsemi.com/ds/J2/J201.pdf

Take a look at the "Transfer Characteristic" shown at the top left of page 3.

This tells you how much ID you get for a given VGS (assuming VDS is held at some constant value)  and I'm ignoring the fact that there are quite large variances in the curves for actual devices (this is important in reality but just bear with me).

Take the curve for VGS(OFF)=-4.5V at TA=25 decgrees C as an example.

Lets say that you want a quiescent value (i.e. the DC bias conditions) of drain current ID of 10mA.  Draw a line across from 10mA to where it crosses the curve and then drop down to the corresponding value of VGS.  You should see that value of VGS for an ID of 10mA is approximately -2.0V. 

Now keep this in you mind for a minute and consider the following: 

The gate is grounded and so VG i.e. absolute voltage at the gate is 0V.
The value of voltage at the source i.e. VS depends on the source resistor (R3 in the case of the circuit shown) and the value of ID i.e. simple ohms law:

........................................VS = ID x R3

from which:

........................................R3 = VS / ID

Now VGS is the voltage difference between the gate and the source i.e. VG - VS

*but* as VG = 0 then VGS = - VS, so

........................................R3 = - VGS / ID


We want ID = 10mA and VGS = -2.0V therefore

........................................R3 = - (-2.0) / 10mA = 200 ohms.

So a value of 200 ohms for R3 in this case would set the quiescent value of ID to 10mA.


In practice, things are not so simple because of the variance of an individual JFET device from the typical characteristic shown in the datasheet.

There are ways to combat this though.  This is probably the subject of another article, but suffice to say that in a lot of JFET designs "R3" is set to a typical value which will provide a typical value of ID and a drain trimmer is used to adjust the voltage at the drain to the voltage required.  There are better ways to stabilise bias though...

[wampcat1]

this needs to be in the wiki!!

bw

[newbie builder]

Brett-
I wasn't thinking right at first, it does make sense that current would decrease as the gate looks increasingly negative (and that voltage would as a result drop)- just had a brain fart is all. I was looking at the J201 datasheet, and was wondering how you would go about finding its transconductance? I saw the two graphs of transconductance vs. VGS and vs. VDG, but wasn't sure how you could estimate the transconductance (is gm the short name? It's starting to get hard to type transconductance so many times!).

This is probably the subject of another article, but suffice to say that in a lot of JFET designs "R3" is set to a typical value which will provide a typical value of ID and a drain trimmer is used to adjust the voltage at the drain to the voltage required.  There are better ways to stabilise bias though...

Thank you for this extremely informative post! My only question is what is a "typical value" of ID? After your explination I was able to look at the datasheet for the J201 and follow everything you said clearly, so I'm just wondering what a value one might chose as an ID value to try to achieve.

Thanks!!
Evan

[db]

My only question is what is a "typical value" of ID? After your explination I was able to look at the datasheet for the J201 and follow everything you said clearly, so I'm just wondering what a value one might chose as an ID value to try to achieve.

There are a number of influences on the choice of ID.  This list probably isn't comprehensive

1) current consumption!

Firstly, you would probably not choose to have a quiescent ID of 10mA in practice because that is quite a drain on a 9V battery.  I tend to bias my designs to less than 500uA for this reason alone.

2) voltage gain

quiescent drain current ID (by the way it is usual to refer to ID or VGS or VD in capitals to represent DC conditions with Id, Vgs for absolute signal levels and id, vgs etc for small signal variations about the DC operating point i.e. your guitar signal) influences gain in an indirect way. 

VD (the DC drain voltage) is:

........................................VD = Vsupply - ID x Rd.

From which:

........................................Rd = (Vsupply - VD) / ID.

Usually you want to set VD to allow the JFET's drain to be able to swing up and down by roughly equal amounts.  For argument's sake, lets assume this is 6V.  So:

........................................Rd = (9V - 6V) / 10mA (using the previous example) = 300 ohms.

So you would have to set Rd to 300 ohms to have the drain sitting nicely at 6V.

But there's another factor. 

The gain of the stage (assuming that you bypass the source resistor with a capacitor for higher AC gain) is approximately:

........................................Av (voltage gain) ~ - gm x Rd. (the - sign accounts for the phase inversion in the drain voltage vd).

The transconductance of a J201 is around 0.5 mA/V or 0.5 mS, so the gain would be about:

........................................Av (voltage gain) ~ - 0.5mS x 300 = 0.15 or about -17dB !!!!. i.e. not much gain, in fact loss.

So it is clear that we have to increase Rd as we cannot change gm significantly without using a different device.

Let's work backwards.  Suppose we wanted a gain Av of 20dB or 10.  Re-arranging the equation a little:

........................................Rd = -Av / gm

........................................Rd = -10 / 0.5mS = 20Kohm !!

So we need a drain resistor of 20K.  This obviously sets the drain current because if you remember, we want the drain to sit at 6V so,

........................................ID = (Vsupply - VD) / Rd.

........................................ID = (9 - 6) / 20K = 150uA.


So, there you have it.  To get a gain of 20dB we need to set ID to 150uA.  You would need to adjust Rs to achieve this as described earlier.


BTW you asked about gm and transconductance.  They are the same thing and are a measure of id versus vgs (note the small letters to denote small signal variations about a quiescent operating point).  Basically, it is the slope of the transfer characteristic on the datasheet.  It's best to have a look, get out a pencil and ruler and draw a line at a tangent to the curve.  Note that gm IS NOT constant.  It varies between device and depending on where you bias an individual device.

[R.G.]

It's worth noting that all JFETs have a maximum drain current that they will allow through. This is noted on the datasheet as "Idss", meaning I (current) from drain to source, with gate and souce shorted.

You MUST pick a target drain current less than the Idss value and greater than 0.

The JFET covers the range of 0 current to Idss through the drain-to-source channel while the Vgs value goes from Vgsoff to 0V.

Vgsoff is the datasheet parameter which specifies the reverse voltage on the gate with respect to the source which makes the drain current less than some low number of nanoamperes.

Since Id goes from 0 to Idss as Vgs goes from -Vgsoff to 0, you might assume that the transconductance is Idss/|Vgsoff|. And it is, if you are in the business of making massive swings on the JFETs. However, the actual small signal transconductance between the two endpoints varies, being lower than this large signal average near cutoff and higher near Idss.

[newbie builder]

Thank you very much Dave, Brett, and R.G- those explanations helped a lot! I really appreciate the help.
-Evan

[db]

this needs to be in the wiki!!

bw

Please feel free - I would add it myself but I don't think I have the correct priviledges.

[newbie builder]

There are ways to combat this though.  This is probably the subject of another article, but suffice to say that in a lot of JFET designs "R3" is set to a typical value which will provide a typical value of ID and a drain trimmer is used to adjust the voltage at the drain to the voltage required.  There are better ways to stabilise bias though...

Sorry to pry further, but I was just experimenting with some J201s and was wondering if you could elaborate on what ways there better ways there are to stabilize bias and combat the variations from JFET to JFET.

Thanks-
Evan

[brett]

Hi

what ways there better ways there are to stabilize bias

there are quite a few, but we often ignore them because for DIY stompboxes it is easy (but not necessarily better) to just use a trimmer on the source or drain.

For almost the whole box and dice on biasing JFETs, check this out:
http://www.colorado.edu/physics/phys3330/phys3330_fa05/pdfdocs/AN102FETbiasing.pdf

It might seem pretty heavy at first, but it really covers the concepts.  Also, most of us here stay with the simple approach of "self" bias, so if you "get" that one, you've got 99% of JFETs covered.
cheers

[db]

Hi

what ways there better ways there are to stabilize bias

there are quite a few, but we often ignore them because for DIY stompboxes it is easy (but not necessarily better) to just use a trimmer on the source or drain.

For almost the whole box and dice on biasing JFETs, check this out:
http://www.colorado.edu/physics/phys3330/phys3330_fa05/pdfdocs/AN102FETbiasing.pdf

It might seem pretty heavy at first, but it really covers the concepts.  Also, most of us here stay with the simple approach of "self" bias, so if you "get" that one, you've got 99% of JFETs covered.
cheers

I would point to the same document - very good reading.

I don't use drain trim pots for the following reasons:
1) The drain trimmer tries to compensate for random variations in bias from one device to the next to get the drain voltage in the right ball-park rather than solve the problem of stabilising bias,
2) drain current isn't very well controlled,
3) gain isn't very well controlled,
4) trimmers are expensive, and take up a lot of space
5) trim pots require "trimming"

In my opinion, I don't think there is a single advantage to the drain trim method of adjusting JFET amplifier stages (other than it *seems* easy to do).

[Jittery]

Just a quick thankyou to those who contributed to this thread.

Especially R.G. - the explanation of "depletion mode" as it relates to JFETs really helped my understanding of what is going on. 

cheers,
jittery / bruce

[beatstrat]

Another vote for inclusion in the Wiki - great stuff guys.

[alanlan]

It's already in:
http://www.diystompboxes.com/wiki/index.php?title=TechTips#Transistors
who is db anyway (shown as a guest)

[nisios]

i think i got it now.

Just to be shure this are some conclusions i took:

Selfbiasing establishes itself at an unknown point.....both voltage and current as they are related obviously, without interference from the drain resistor.

If we increase drain resistance we get more gain and lower current (but the self bias adjust to this condition...thats why we say this resistance doesnt affect the biasing)

Now some questions:

How do we know the value of the drain voltage that allows more voltage swing?

How do we predict even aproximatelly the gain of the circuit?

How the hell does increasing the source resistor contribute to attenuate the overall gain? and what are some good values for this resistor?