An overdrive/distortion.... A little different, this one.

[gez]

Oh yeah, and parts LEFT OUT of the output buffer by some guy who was asleep at the design desk.

From mistakes do great things occur! 

[jaytee]

Can this be done with 2 discrete mosfets? I still don't understand how these things work by just biasing with a single resistor. I wonder if it would work with 2 jfets?

[gez]

Can this be done with 2 discrete mosfets?

Yes, but personally I wouldn't (reasons given in a link in another active thread at the moment).

I still don't understand how these things work by just biasing with a single resistor.

Explanation given in said link (plus other links in other threads)

I wonder if it would work with 2 jfets?

No.

[jaytee]

What thread is that in?

[gez]

What thread is that in?

Here's a direct link to the info:

http://www.diystompboxes.com/smfforum/index.php?topic=17114.0

Apologies for not posting it earlier but I didn't have the time.

To understand the workings I'd recommend you take a look at the datasheet for the 4049 and hunt around in it for the schematic of an inverter, then read through the above. 

If still not clear, think of the following: inverters invert.  So, at switch on, if the output is high and the input is low, the output is going to pull the input up as there's a resistor attached between the two; this, in turn, pulls the output down (inverters invert remember).  The input can't be pulled up higher than the output as the output, if it dips lower, would pull the input down with it...which causes the output to go high again (what do inverts do?).  The end result of all this is that the output and input will sit at exactly the same voltage. 

Next, think about RG's analogy of the p-channel and n-channel devices (often referred to as a 'totem pole' - and for obvious reasons when you see the schematic) as being like two voltage controlled resistors stacked on top of each other.  If you bear in mind that the devices are matched (equal resistance) then it's easy to see that 'self-bias' results in the inputs and outputs sitting around half supply.

[jaytee]

Thanks for explaining I get that. I guess it would be more difficult to bias if the fets wern't matched? Would it work to put a potential divider at the input to bias it?

[gez]

My own experience of discrete inverters is that clipping isn't that soft.



Can't remember what values were used for the source resistors, or whether I bypassed them...lost in the mists of time!

[puretube]

Sir Paton: allow - now you got me completely puzzled with that schem! 

the way I see it, is
(assumed the wire-cross between the 100k max feedbackresistor/22µ cap/100k trimpot/1M drive-pot indeed is a node)
that DC-wise the 100kmax FB-resistor does indeed establish an exact "Ub/2" bias at in- & output, as is taught in the schoolbooks,
which might be able to be pulled away from half supply either way by the 100k trimpot,
BUT: any AC signal to be fed back from the out- to the input through that "100k max" /and hence limit the maximum gain (A= R_FB/R_IN) is being shunted to ground by that 22µ capacitor before it gets combined with the inputsignal,
such that the circuit will always be working at its maximum possible physical gain (let`s assume 50 - 70 times), independant of the value of that FB-resistor,
and the actual amplification factor of the circuit isn`t being defined by the R_FB/R_IN ratio,
but only by the attenuation of the inputsignal through the 1M pot.

(err: they say my posts are meaningless rubbish, lately, and ask why I do post here anyway, but this time I thought: what the heck - freedom of speech - let`s just try, write, and ask...  )

[(edit):   hey: and congrats and welcome to the 5k⁺ club!  ]

[gez]

[(edit):   hey: and congrats and welcome to the 5k⁺ club!  ]

Wow, I hadn't even noticed!  Is that like the 5 mile high club??

Sir Toob ( ), your analysis is correct.  AC feedback is decoupled by the 22u cap so the amp is run at full pelt and gain is controlled via the 1M drive control (which simply attenuates the signal).

The 100k trim does indeed bias unmatched MOSFETs (for symmetrical clipping).  The 100k resistor is in parallel with the output resistance of the inverter and changing its value effectively controls gain by loading to a lesser or greater extent.  However, it should be no bigger than 100k as the 22u cap will take too long to charge up and bias the (discrete) inverter...besides, any greater value will have little effect on gain.

I don't know why I typed all that, I just rewrote what you said in your post! 

[gez]

(err: they say my posts are meaningless rubbish, lately, and ask why I do post here anyway, but this time I thought: what the heck - freedom of speech - let`s just try, write, and ask...  )

I read you loud and clear.    Well, mostly! ( )

[GREEN FUZ]

(err: they say my posts are meaningless rubbish

Meaningless? Perhaps. Rubbish? Never.

Or is that the other way round?

[jaytee]

I think the gain would be brought down by those source resistors. Bigger resistors, less gain. I was trying to get my head round why the transfer curve gets so bendy near the rails. I think its because the fets are kind of 'upside down'. The souce is at the rails and drains tied together. Biased half way theres 4.5v gate-source. An input signal would turn the fet OFF so you get to that bendy part of the transfer curve near where the fet turns on. Is that right?
Maybe I should start another thread on this one....

[gez]

I think the gain would be brought down by those source resistors.

Yes, that's true.  However, the transconductance of discrete MOSFETs is a lot higher, so reduction in gain is no bad thing.  Having said that, I probably bypassed the source resistors (whatever value was used: note that there are queston marks by them) with large caps.

Unless you're after a booster (which is all that schematic is, as shown) then it's just a hell of a lot easier to use ICs...less components and it's well trodden territory (results are bound to be good).

PS  I'm pretty sure I included the source resistors to reduce current.

[gez]

I was trying to get my head round why the transfer curve gets so bendy near the rails.

Transconductance of each device drops off when pushed into saturation, hence the compression. 

[brett]

Hi

The 100k trim does indeed bias unmatched MOSFETs (for symmetrical clipping)

Or, for asymetric clipping with well-matched inverters like those packaged in a CD4049, you could bias *away* from half of Vsupply.  Biasing to about 1/4 of supply might be interesting.  Have I seen that done somewhere by using a large value resistor pulling the inverter input or output towards ground?
cheers

[gez]

Have I seen that done somewhere by using a large value resistor pulling the inverter input or output towards ground?
cheers

There was a discussion a few years ago about using a trimpot, after which Tim Escobedo incorporated one into one of his designs.  There are also a number of designs with large value resistors to ground to create offsets.  The thing to bear in mind is that if you have offsets further down the line, then it's likely that large signals are going to be driving those stages so there's a danger that the protection diodes on the input will be brought into conduction (no soft clipping).  This only applies if said stage(s) is/are AC coupled: with direct coupling, the output can't swing any lower/higher than the rails...though any offset in one stage creates further offsets in subsequent ones.

[puretube]

some factory-circuits play with resistors-to-ground intensively, too  .

Gez/Brett:
not to derail this thread, I posted the complete schemo  about my interpretation of a discrete "CMOS Inverter Simulator" :



in an extra thread...

to me, soundwise/curvewise it appears as an equivalent to a "Sixth Of Hex"  ,
and is able to bring forth some soft clipping...

the dead-short link-trick from output to input doesn`t work on this one, however 

[brett]

Hi
Has anyone else built this yet?  I like it a lot, and would like to know whether anyone else likes it too.  (IMO its as nice as my Tubescreamer).

Anyway, I took some photos of waveforms today.  I used a fairly hefty input signal (250mV p-p), so the distortion is more than would be achieved with soft playing (and less than would be achieved if used with a booster):



Here's the smooth-o-matic's output, on the same scale, with the gain at "noon":



And the output with the gain at "3 PM":



One thing interests me is that although it is self-biased, it isn't even-sided; the top is "fatter" or "flatter". 

All comments and feedback welcome.

[puretube]

ooops:
sorry, Brett,
still haven`t built it yet...
but while pondering over a problem in another thread  and going through the usual literature,
I remembered (and found) what I was thinking about a few months ago
whith this "Grounded (or: shorted) Inverter Output" thing, and what it had reminded me of at that time:
Cmos OTA,
where Osamu explains the working of a
CMOS VCA
(Mike Irwin-inspired too, I guess...  )

now I`m wondering, what an equivalent Jfet circuit would behave like, when artificially "saturated" (pageing GEZ...  )

...greetings btw., to all my stalkers, from the 6k+ club...

[gez]

now I`m wondering, what an equivalent Jfet circuit would behave like, when artificially "saturated" (pageing GEZ...  )

I haven't progressed to a 2 stage JFET circuit, yet, but I'll give Brett's idea a go when I do!