CMOS inverters as Tubes ??

[dschwartz]

Hi all!!

I´ve been playing with my new hot harmonics and it sounds really amazing!! so...
I am triyng out to make my own design of CMOS based distortion/preamp but theres too few or none theoretical info about CMOS inverters used as amplifier..I can see that´s similar to opamps on inverting mode, but no clue about gain or voicing settings...

is there a formula for gain on these? input impedance resistors? for example, like the fetzer valve..is something like CMOS valve around?

my goal here is to make something like the DR boogie, but with CMOS..using 5 inverters, ang controlling gain on each one..i´m sure it can be done!

[mdh]

You might check out this app note: http://www.fairchildsemi.com/an/AN/AN-88.pdf.  It's been awhile since I looked at it, but I seem to recall it was pretty useful.

[gez]

theres too few or none theoretical info about CMOS inverters used as amplifier.

If you use the search function, you'll find all the info you need.  I'm not being short with you, it'll just save a lot of typing for some here.

[twangquack]

I´ve been playing with my new hot harmonics and it sounds really amazing!!

You're making me jealous! I'm still waiting on the tone control parts (everything else is done). What further nuances have you discovered? (Also, is it a bit of a battery suck? -- you know ... that ol' thirsty CD4049UBE).

my goal here is to make something like the DR boogie, but with CMOS..using 5 inverters, ang controlling gain on each one..i´m sure it can be done!

I'd love to hear what you find out and come up with ... I have several extra CD4049 in my parts bin (and new stripboard -- love Aron's stuff!) and would love to do another CMOS project (besides trying the ROG UBE-Screamer).

[gez]

A few threads that I remember (there are many more):

http://www.diystompboxes.com/smfforum/index.php?topic=11634.0

http://www.diystompboxes.com/smfforum/index.php?topic=17114.0

http://www.diystompboxes.com/smfforum/index.php?topic=20833.0

(schematic for above available at Marcos/Munky's site: called the 'nut cruncher').

http://www.diystompboxes.com/smfforum/index.php?topic=59155.0

http://www.diystompboxes.com/smfforum/index.php?topic=50803.0

I included a few of my own circuits as there's a little theory in the threads, which may be of interest.

[dschwartz]

You might check out this app note: http://www.fairchildsemi.com/an/AN/AN-88.pdf.  It's been awhile since I looked at it, but I seem to recall it was pretty useful.

yeah thanks!! this was what i needed..

GEZ, thanks too...i used the CMOS search..found a lot of CMOS circuits...but too little specifications or theory behind..for example..
why does fet preamps/OD´s use 10 to 47nF coupling  caps, and most CMOS OD´s use 0.1 to 0.47uF coupling caps?

i tried simulating a cmos amp with livewire..but noticed that the output voltage was no bigger than the input voltage (used 74UCH04)..even when in practice this kind of boosters has a lot of volume boost...

[gez]

why does fet preamps/OD´s use 10 to 47nF coupling  caps, and most CMOS OD´s use 0.1 to 0.47uF coupling caps?

Well, you'd have to give an example, but often circuits are derivatives of a 'classic' (whether project book or commercial pedal) so values don't vary much from clone-to-clone.

The value of coupling caps depends upon input impedance and whether you wish to limit bass between each stage.  Different input impedances require different capacitor values, hence the larger values in inverter circuits (impedance tends to be lower in CMOS circuits biased similar to inverting op-amps).

[dschwartz]

hmm...so that´s why.. i assumed that was a legacy from older "fuzzier" circuits ..

so, you say that cmos at linear mode has lower input impedance so:

if Zi  is input Impedance  and Ci an input coupling capacitor.. the low end roll off will be:

f= 1/2*pi*Ci*Zi

if a normal Ci for a FET CKT is 0.022uF, an a normal Ci for a CMOS is 0.22 then:

to make:
f cmos=f fet

then Zi cmos is 10 times smaller than Zi Fets???

AFAIK inverters has very high input Z..is ten times smaller than fets input Z???

[gez]

so, you say that cmos at linear mode has lower input impedance

If biased similar to an inverting op-amp stage (feedback resistor from output to input and and input resistor), then impedance tends to be relatively low.  If you look at the nut cruncher thread linked above, however, you'll see a different way to bias inverters for high gain and high impedance.

if Zi  is input Impedance  and Ci an input coupling capacitor.. the low end roll off will be:

f= 1/2*pi*Ci*Zi

The formula is correct for calculating cut off.  As a rule-of-thumb, designers use the value of the input resistor in the equation you quoted.  In reality, because of the low gain of these amps, impedance is a little higher.  If you wish to do a little more reading, google Miller input impedance/Miller effect/inverting op-amp input impedance.  There's an accurate analysis in the archives somewhere specifically for CMOS inverters.

if a normal Ci for a FET CKT is 0.022uF, an a normal Ci for a CMOS is 0.22 then:

to make:
f cmos=f fet

then Zi cmos is 10 times smaller than Zi Fets???

AFAIK inverters has very high input Z..is ten times smaller than fets input Z???

Although the input impedance of the MOSFET devices within the inverter is 'infinite', the bias method used lowers it considerably.  Again, google the things I mentioned above and the penny should drop.  Gain in most circuits is set (made larger) by making the input resistor smaller in comparison to the feedback resistor.  This means that to get decent gain there's a trade-off in input impedance (it ends up being low).  There's no hard-and-fast rule involved that says 'just increase the caps by X times and all will be well', you have to take things on a case-by-case basis; working with the values you have chosen in your design.

[dschwartz]

thanks gez

i´ll be posting the results of my breadboard experiments with cmos distortion...

i think that all the cmos OD´s  circuits around are "cousins"..and dont go any step further..