CD4069 vs CD4049 driving an LED

[mdh]

I've been playing around with one of the Tone God's wicked switches, using a CD4069 to build a flip-flop and drive an LED.  I've noticed, however, that both Andrew and R.G. recommend the CD4049 for this purpose, and I was wondering whether there is some reason why the 4049 is better than the 4069 here.  I've looked at the data sheets, and I get the impression that the 4049 can handle more power, but I'm not sure which spec to look at to determine whether I'm operating within specifications.  It's hard to imagine that it would take much current to operate the switch, so I'm more concerned about the LED.  I estimate that I'm drawing about 6 mA from the gate that's driving the LED.  The circuit in question is here: http://www.geocities.com/thetonegod/switches/switches.html; momentary with inverter gates, about 3/4 of the way down the page.  It's pretty much the same as R.G.'s inverter gate flip-flop in his CD4053 article.

Can anyone educate me on how to get the information I want out of these datasheets?

[mdh]

Hmm... I think maybe I've figured this out on my own, but I would appreciate it if someone could confirm or refute my conclusions.  Here's a schematic of the LED portion of the circuit:



So the LED is lit when the input is high.  At +9V supply voltage, this should result in 7 mA through the LED. In practice, I'm getting about 6 mA, because my battery is a little low, and the output of the inverter is actually showing about 0.75 V when low (other outputs are at ground potential when low; is this an indication that I'm drawing too much current?).  As far as I can tell, the relevant rating on the data sheet is I_OL, low level output current.  It seems like the appropriate numbers to look at are 2.25 mA (V_DD = 10 V, V_O = 0.5 V) and 8.8 mA (V_DD = 15 V, V_O = 1.5 V) for CD4069.  The CD4049 data sheet indicates that I_OL should be kept below 12 mA for extended periods, but peak currents can be higher.

What I'd really like to understand a little better is the relationship between V_O and I_OL, and to know definitively how much current I can safely draw from an inverter.  One thing that sort of confuses me is that the V_OL specification is 0.05 V max for all temperatures and supply voltages, whereas the data sheet indicates values of I_OL for values of V_O greater than 0.05.

I suppose that if I can't safely get enough current from an inverter (or two in parallel), I'll just use a transistor to drive the LED.

[R.G.]

OK, you did the important part first - you got the datasheets. You've even identified some of the important parts.

For the CD4049B (buffered), I'm using National Semi's version. It comes in both buffered (BCJ) and unbuffered (UB) versions. For the 4069, I'm using Fairchild's datasheet.

You want to pull substantial (for CMOS) current to ground, so you want to know how low can the inverter pull its output pin for X current. The place that's listed most closely is Iol - output current at a low logic level. For the 4049 it shows that Iol can be a peak of at least 6.2ma and "typically" 12ma **IF** you have a 10V power supply  (we don't, but 9V is pretty close) and if you don't care if the output pin voltage Vol rises to 0.5V. That is, when the output is low, it looks like a 42 ohm resistor to ground.  You're guaranteed that it's no worse than 0.5V/6.2ma = 81 ohms.

But then there's that pesky (note 3) which says "These are peak output capabilities. Continuous output current is rated at 12ma maximum. The output current should not be allowed to exceed this value for extended periods of time. Iol and Ioh are tested one output at at time.".

That's their way of telling you "You'll fry the output drivers if you let this go on forever. The outputs can only handle 12ma max for long periods of time. Oh, yeah, we don't tell you anything about the package maximum, only one pin at a time." And there's a limit of 700mW dissipation for the entire package. Putting out 12ma on each output with 0.5V on the output pin is 36mW, so that's OK. So you can definitely pull 12ma to ground on one or all outputs of a CD4049 forever. I'm ignoring the 9V vs 10V difference in power supplies.

The Vol spec which confuses you is further up the spec sheet and it notes in the conditions column that the Iol for that spec is less than 1uA. You start with an Iol that's thousands of times bigger, so you have to go to the Iol lines. All of the specs on a spec sheet are not true at all times, only under the noted conditions for that one test.

For the 4069, Iol at 10V power supply and 0.5V output voltage is minimum 1.3, max 2.25ma. So the 4069 will only pull about 1/5 of the current to the same voltage as a 4049. The 4049 is five times as "strong" for pulling current in through an output pin to ground.

Reading datasheets is an acquired skill and not an easy to see trick. The manufacturer warrants A MAXIMUM of performance of what's on the datasheet, with all of the caveats you can find anywhere in it. There are many pitfalls - like ever believing you'll get any parts that measure "typical". Assume in reading a datasheet you're reading an insurance policy where the company is trying to write in loopholes and legal strategems to get out of paying off.

[mdh]

Thanks, R.G., that clears some things up.  So if I have an inverter whose output is low, I can measure the actual V_OL, and pretend that the output is a resistor dropping that much voltage to ground.  Since I know what's going on in the rest of the series circuit, I know the current, so I can calculate how much power I'm asking that inverter to dissipate.  But here's the thing:  you say the 4049 "pulls" more current (so it has a lower series resistance) than the 4069, and that the whole package can dissipate 700mW (the 4069 data sheet gives the same number).  Now, I know from measuring an actual circuit on the breadboard that the gate driving the LED is pulling 6mA.  But as far as I can tell, they don't tell me how much power each inverter can safely dissipate, which is what I'm concerned about.  If I understand correctly, this means that the gate that's driving the LED on my 4069 looks like a 125 ohm resistor (0.75V/6mA), so it's dissipating 4.5mW.  Now, if I measure the voltages on the other gates (which, recall, are pulling flip-flop and 4066 switch control duty), they're never more than 0.05V from the supply voltage or ground, so it seems that each of those gates is dissipating a negligible amount of power.  If this is really the case, it would seem that I can draw 6mA from that one gate forever.  Is that correct?

Is there any rhyme or reason (aside from the CYA rationale that you cited) governing the scenarios that are listed on the data sheet?  E.g., on the Fairchild 4069 data sheet, they give I_OL values for supply voltages of 5V, 10V and 15V with V_O = 0.4V, 0.5V and 1.5V, respectively.  But that's just one point along some curve for each of those supply voltages, so it's really not much information (the Fairchild sheet, at least, doesn't contain a graph for this characteristic).  If I calculate the equivalent resistance for each of the minimum/typical I_OL values given, I get values ranging from 170 to almost 1k ohms, but of course, as I said above, it looks more like 125 ohms in my circuit.  If I do some wild approximating, and assume, say a 1k ohm resistance as a worst case scenario, then 20mA would get me 400mW of power dissipation for that one gate, at which point it seems like I definitely should start to get worried.  Am I missing something critical in these calculations, or do I have the right idea?

[R.G.]

Thanks, R.G., that clears some things up.  So if I have an inverter whose output is low, I can measure the actual V_OL, and pretend that the output is a resistor dropping that much voltage to ground.  Since I know what's going on in the rest of the series circuit, I know the current, so I can calculate how much power I'm asking that inverter to dissipate.  But here's the thing:  you say the 4049 "pulls" more current (so it has a lower series resistance) than the 4069, and that the whole package can dissipate 700mW (the 4069 data sheet gives the same number).

The dissipation number is a characteristic of the physical package, so all 16 pin DIPS should be very close to that if the internal construction is similar. There are several different limits: (1) how much current can the bonding wire between the silicon package and the actual external pin carry? (2) how much current can the transistor on the chip doing the pulling actually pull? (3) for both of those, for how long? (4) even if the current's OK, does the (a) entire chip or (b) just that section overheat? (5) if many outputs are pulling full current, can the +V and ground pins stand the total current? The actual limit is the most restrictive of all of these for the circuit in question.

Now, I know from measuring an actual circuit on the breadboard that the gate driving the LED is pulling 6mA.  But as far as I can tell, they don't tell me how much power each inverter can safely dissipate, which is what I'm concerned about.

They don't tell you that, do they? About all you can do is assume that any single inverter can dissipate it's prorata share of the whole package; in this case 117mW. But it's a guess.

If I understand correctly, this means that the gate that's driving the LED on my 4069 looks like a 125 ohm resistor (0.75V/6mA), so it's dissipating 4.5mW.  Now, if I measure the voltages on the other gates (which, recall, are pulling flip-flop and 4066 switch control duty), they're never more than 0.05V from the supply voltage or ground, so it seems that each of those gates is dissipating a negligible amount of power.  If this is really the case, it would seem that I can draw 6mA from that one gate forever.  Is that correct?

That's correct. Well, at least that's how I'd approach it.

Is there any rhyme or reason (aside from the CYA rationale that you cited) governing the scenarios that are listed on the data sheet?  E.g., on the Fairchild 4069 data sheet, they give I_OL values for supply voltages of 5V, 10V and 15V with V_O = 0.4V, 0.5V and 1.5V, respectively.  But that's just one point along some curve for each of those supply voltages, so it's really not much information (the Fairchild sheet, at least, doesn't contain a graph for this characteristic).

Yep. Some datasheets give curves, some give points. It's really, really hard to write a datasheet that is both complete and accurate. If all of the info was there, the datasheet would be a hundred pages or more. 5V, 10V, and 15V are common voltages for industrial use of CMOS. 9V is our own cross to bear in this backwater. And we are a backwater.

If I calculate the equivalent resistance for each of the minimum/typical I_OL values given, I get values ranging from 170 to almost 1k ohms, but of course, as I said above, it looks more like 125 ohms in my circuit.  If I do some wild approximating, and assume, say a 1k ohm resistance as a worst case scenario, then 20mA would get me 400mW of power dissipation for that one gate, at which point it seems like I definitely should start to get worried.  Am I missing something critical in these calculations, or do I have the right idea?

You're missing something critical. The output transistors on that inverter are MOSFETs which approximate voltage variable resistors. With only 5V available to turn the top or bottom one on, it can only change down to maybe 1K. So it cannot hold Vol <= 0.5V except at very low Iol. Remember - the unstated assumption here is that the LOGIC inverter will be driving LOGIC gates which will in general be far less than 1uA of current each. They write that datasheet for LOGIC designers, not analog designers. I'm putting an analog designer's spin on the data so I have something, however poor, to design with.

When you get more power supply voltage, like 10V, you have more voltage to turn the output devices on harder, and they "saturate" to lower resistances. Even more at 15V.

The thing to remember about switching logic is that it's usually low power when it's fully switched. It's when it's in the middle of its swing that there's a lot of power being dissipated. We try to keep the middle of the swing short to keep from burning things up.

Sorry about the cynical view of datasheets, but you'll do better design if you start from a pessimistic view of what a maker tells you his stuff will do.

[mdh]

Excellent.  Sounds like I'm on the right track overall, with caveats.  In a way, it's kind of a lame thing to get hung up on, but sometimes I get curious about the most mundane things, and I'm not happy until I understand them.

If I calculate the equivalent resistance for each of the minimum/typical I_OL values given, I get values ranging from 170 to almost 1k ohms, but of course, as I said above, it looks more like 125 ohms in my circuit.  If I do some wild approximating, and assume, say a 1k ohm resistance as a worst case scenario, then 20mA would get me 400mW of power dissipation for that one gate, at which point it seems like I definitely should start to get worried.  Am I missing something critical in these calculations, or do I have the right idea?

You're missing something critical. The output transistors on that inverter are MOSFETs which approximate voltage variable resistors. With only 5V available to turn the top or bottom one on, it can only change down to maybe 1K. So it cannot hold Vol <= 0.5V except at very low Iol. Remember - the unstated assumption here is that the LOGIC inverter will be driving LOGIC gates which will in general be far less than 1uA of current each. They write that datasheet for LOGIC designers, not analog designers. I'm putting an analog designer's spin on the data so I have something, however poor, to design with.

When you get more power supply voltage, like 10V, you have more voltage to turn the output devices on harder, and they "saturate" to lower resistances. Even more at 15V.

Point taken (well, many points, really).  I was trying to be conservative by assuming 1k ohms... I figured it would probably be lower for higher supply voltages (though I didn't know why... I just noticed that the resistances were higher for 5V than 10V and 10V than 15V).

The thing to remember about switching logic is that it's usually low power when it's fully switched. It's when it's in the middle of its swing that there's a lot of power being dissipated. We try to keep the middle of the swing short to keep from burning things up.

Huh, good point.  I hadn't thought about the transients, which is sort of funny, since my day job involves studying transients in a different sort of (biological) system.

Sorry about the cynical view of datasheets, but you'll do better design if you start from a pessimistic view of what a maker tells you his stuff will do.

No, no, informed cynicism is always welcome.  This is good perspective.  You've given me a lot to chew on.  Thanks.