Methods for handling unmatched JFETs in a circuit needing matched

[gaussmarkov]

Rod Elliott has a vibrato circuit that accounts for mismatched JFETs.  It's called the Guitar Vibrato Unit.  A general approach like this would be useful in lots of other circuits.  Can anyone describe the design issues involved?  Are there several ways to do this?

Thanks in advance, gm

[Mark Hammer]

This method strikes me as being more useful in the vibrato context than in the phaser context.  The chief reason is that one expects/needs significantly less sweep range from a vibrato than from a phaser, and the very reason one tries to match FETs in a phaser is so that all control elements (i.e., FETs or LDRs) continue to show change at all points in the generally much-wider sweep cycle, as opposed to sweeping 75% of the way and then grinding to a halt for the remaining 25% of the LFO's sweep.

Here, not only is there less error and inconsistency of sweep to manage due to the narrower range of sweep needed (and remember it's easier to match FETs if the sweep range is more restricted), but given the use of only 2 stages, there is greater likelihood of aligning all the required stages.  Where one is aiming for 4 or more stages that need to move in synchrony in order to create moving notches, the matching needs to be more precise.

Having said THAT, if one was purely interested in a narrow-speed range, narrow-width phaser - for example one set to mimic fast Leslies only - this sort of a solution like Rod suggests could work quite nicely.

make sense?

[gaussmarkov]

o.k.  thanks mark!  i'm going to throw out another thought and further expose my ignorance.    i am hopeful that you or someone else will comment.

i went off and read some more about JFETs as variable resistors and found some stuff on the ohmic/triode/nonsaturated region where all the action is.  no one said this explicitly in what i read but i infer that Vgs (gate-source voltage) must lie between 0V and Vgs(off), a.k.a. Vp for pinch-off voltage.  from reading geofex.com, it is the Vgs(off) that varies a lot from JFET to JFET.

if we measured Vgs(off) for each of our JFETs, and knew the minimum and maximum voltages of our LFO, could we not insert an amplifier at each JFET's gate so that it's voltage varied only over the range 0V to Vgs(off)?  would this handle the differences in JFETs within our circuit?

if this could work, i suppose that we would not have to literally measure Vgs(off) to calibrate appropriately.  and maybe it's not an attractive solution, given that one can just go and find matches as described by R.G. on geofex.com.  now i'm just caught up in the idea of adjusting a circuit to meet the problem.  and if this sort of thing does work, then maybe there's a more attractive way to do it.

cheers, gm

[gaussmarkov]

one additional thought down this road.  if the LFO amplitude is large enough, which i think it can be with a 9V supply, then it's just a matter of attenuation.  no amplification needed.  so then as long as the LFO has a low impedance output, all that will be required is a voltage divider.

i know it just cannot be that easy.    but i don't know why.

[gaussmarkov]

more research and some simulations suggest to me that this is not so crazy an idea.  it's success would depend, in part, on the stability of Idss, drain current with Vgs=0.  if that is moving around as well as Vgs(off) then there's a problem at the other end of the Vgs range as well and there's too many problems to fix with a simple voltage divider.

comments welcome! 

[Paul Perry (Frostwave)]

It's one thing to get the turn on voltage of the fets matched - which this circuit does - but what about matching the effective resistance at any voltage?
I don't personally think that this 'matches' the fets as well as one would want. (I'm prepared to be shown that I'm wrong, though - I'm not an EE!)

Considering that quite a lot of trouble is caused to DIYers by using even SINGLE fets - as in the EA trem - I think the best thing to do with matched fets, is to design them out of the circuit, by using pulse width modulated switched resistors, for example.

[George Giblet]

The effective resistance is given by,

             rds(Vg) = rds0 / (1+Vgs/|Vp|);  where Vgs <= 0

As it turns out rds0 = 1/Yfsmax is the easiest JFET parameter to control.  For the same batch rds0 is quite close from device to device, but it may vary say 2:1 over all batches.  Most amplifier JFETs have a similar rds0.  The switching types tend to have lower rds0.

If you bias the Jfet at Vp and add a control voltage Vc you get,

              rds(Vc) = rds0 / Vc

What that means is once you bias the JFET the effect of Vp is removed.  Since rds0 is fairly close from unit to unit that means adjusting the control voltage level to each JFET is often unwarranted.  Moreover most circuits will function fine with some mismatching in rds.

Bottom line is individual biasing adjustments on JFETs can help.  What you are trading off is sorting Vp's at the start for more trimpots on the PCB and a more difficult adjustment procedure.

[gaussmarkov]

Considering that quite a lot of trouble is caused to DIYers by using even SINGLE fets - as in the EA trem - I think the best thing to do with matched fets, is to design them out of the circuit, by using pulse width modulated switched resistors, for example.

this is the first that i have heard of "switched resistors."  it took me a while to figure out that another term for them is "digital potentiometers."  if i understand what you are suggesting, then we would insert a VCO to take the LFO into the switched resistors.  i guess this would require a "clock" as well.  i am thinking of the sort of arrangement that i have seen in an electric mistress.

[gaussmarkov]

The effective resistance is given by,

             rds(Vg) = rds0 / (1+Vgs/|Vp|);  where Vgs <= 0

As it turns out rds0 = 1/Yfsmax is the easiest JFET parameter to control.  For the same batch rds0 is quite close from device to device, but it may vary say 2:1 over all batches.  Most amplifier JFETs have a similar rds0.  The switching types tend to have lower rds0.

If you bias the Jfet at Vp and add a control voltage Vc you get,

              rds(Vc) = rds0 / Vc

What that means is once you bias the JFET the effect of Vp is removed.  Since rds0 is fairly close from unit to unit that means adjusting the control voltage level to each JFET is often unwarranted.  Moreover most circuits will function fine with some mismatching in rds.

Bottom line is individual biasing adjustments on JFETs can help.  What you are trading off is sorting Vp's at the start for more trimpots on the PCB and a more difficult adjustment procedure.

so this sounds simpler than what i was thinking.  i was worrying that Vgs might wander positive so that the LFO would need to be adjusted for each JFET.  here's a representation of the mxr phase 90:



if i understand, all that would be required for your suggestion is to put in a separate trimmer, resistor, and capacitor for each JFET's gate so as to bias each JFET at its Vp.  is that right?

cheers, paul

[Mark Hammer]

It may be a reflection of my own lack of knowledge, but digital pots are not the exact same thing as switched resistors.  In the case of the former, the digital code sent to the chip may be used to establish which of a network of resistors are switched into circuit to either provide some fixed attenuation or perhaps alter a control current for a VCA.  The idea is that one can know in advance the impact of the code on gain or attenuation.  In the case of switched resistors, one is using the overall average resistance value over time as the effective value.  perhaps the best known case here would be the way in which on/off time of some CMOS switches is used to vary the effective resistance of key areas in the filter structure of the MXR Envelope Filter.  If the switch spends more time off than on, the average resistance value is closer to open circuit (or whatever the max resistance is of the solid-state switching element when off/"open").  If it spends more time on than off, the average value over time is closer to that of whatever fixed resistor/s might be in series or parallel with it.

A kissing cousin of this is the switched capacitor arrangement which is found in those sweet filter chips from NatSem like the MF6 http://www.datasheetarchive.com/pdf/2319977.pdf , and MF10 http://www.national.com/mpf/MF/MF10.html  There, the average capacitance value over time is what one is varying.

And yes, both are ultimately dependent on a HF clock of some kind. 
Assuming one has significantly more PIC knowledge than I do (though brother Keen has vowed to lift me out of my misery and ignorance on that count ), interesting digital control of an analog circuit could be accomplished.  Essentially, you have two virtual clocks, one virtual LFO modulating a second HF clock, with the resulting output switching FETs at high speed.

You do realize you don't NEED to use FETs, but can apply the switched resistance strategy without them at all?  Steve Giles has posted his redraw of one of the pre-closure (i.e., early-to-mid 80's) MXR phasers that used CMOS switch sections instead of FETs, though I'm damned if I know where.  There, instead of a FET to ground, one has a fixed resistor, and a 4066 or 4016 section hooked to a master clock circuit where an LFO modulates pulse width of a HF clock.

[gaussmarkov]

i am completely in the dark about both "switched resistors" and "digital pots" so having found no parts called "switched resistors" i made a mistaken inference.     mouser has lots of the latter and nothing comes up under the former.  everything else i found on the internet made no reference to a particular device.

what are some specific devices for switched resistors?  any app notes out there about switched resistors?

[gaussmarkov]

oh!  maybe this is a technique and not a component.  that would make mark's description more understandable. 

[Mark Hammer]

Ko-rect-o-mundo my friend.  Digital pots are a component that entails a certain approach.  Switched components are a general technique that can use any of a variety of components.

You can use whatever the heck you want for switching.  Heck, if you could find a relay fast and quiet (and durable) enough, you could use THAT for high speed switching of components to effect an "average" value.  The preferred technique, however, seems to be use of CMOS switches because they are silent, durable, easily matched, fast and cheap like borscht.  Compare the cost of a CD4066 with 4 switches on board to a quartet of suitable FETs.

To learn a wee bit more about how one might use switched components, I can think of no more illustrative a place to look than the very clever uses that MXR made in the late 70's and early 80's.  The green Analog Delay, later copied by Ross, used switched resistors to produce a "tracking filter" that adjusted wet signal for maximum bandwidth in synchrony with delay time.  One master clock was used for the BBDs, but divided down differently for the tracking filter system so that it trimmed more high end as delay got longer (and risk of audio crap got higher).  Simply brilliant.  See it here: http://img.photobucket.com/albums/v474/mhammer/MXRAnalogDelayschem2.png  and here:  http://img.photobucket.com/albums/v474/mhammer/MXRAnalogDelayschem1.png

[gaussmarkov]

this is so cool.    i am eternally in your debt.  hmm.  i've probably already said that on another occasion.  and you cannot have my first born (already promised to R.G.).  well, i will think of something. 

will this concept work with a passive RC filter and an audio signal?  say i switch rapidly between two different filters -- do i get a combination of the filters as what's actually heard?  i'm gonna guess not but maybe our hearing fools us.  it sures pays to have a psychologist on the forum.

[George Giblet]

I made an error in my post the other day (brain dead from lack of sleep over the last few days).

>    rds(Vc) = rds0 / Vc

Should be,

rds(Vc) = rds0 / (Vc/|Vp|)

So you do need a Vp scaling factor.  When you match JFETs you match Vp and so the Vp scaling factor matches on each stage - that's another advantage of matching Vp's.  However, as I stated if you adjust the bias point for at Vp for individual JFETs the |Vp| scaling factor isn't a big deal in most circuits.


> if i understand, all that would be required for your suggestion is to put in a separate trimmer, resistor, and capacitor for each JFET's gate so as to bias each JFET at its Vp.  is that right?

Yes you need a separate trimmer for Vp, a separate series Resistor for mixing the bias with the LFO and as it stands a separate cap.  You might be able to use a lower series R and a single C to ground for the LFO then from that point a larger R which mixes the LFO and Vp bias.  That would save caps on each stage.   

As you can see a 6-stage phase is getting complicated - probably a good reason to match Vp's and use a simpler circuit.

[gaussmarkov]

thanks george.  i appreciate you following up on this line of thinking.

it was started by thinking about a vibrato circuit that has two stages.  so it would certainly be workable
there.  and it seems to me (though i might be corrected) that the overall method could end up working
better than "matched" JFETs.  by working off the range of the transistors ohmic region, rather than the Vgs
at a particular resistance, one is guaranteeing that no single resistance quits changing over the entire cycle
of the LFO.

if Idss does not vary much over JFETs then there wouldn't be much difference.  but if it does, then it is at
least possible that the difference would be large and the problem that mark hammer mentions, a VCR
stopping prematurely, would occur more frequently with JFETs matched at one point.

of course, one could always refine the JFET matching to matching at several resistances.  then you might
have to have a lot of JFETs to get matches that are comparable to the effect of translating and scaling
each gate.

cheers, paul

[George Giblet]

>one is guaranteeing that no single resistance quits changing over the entire cycle
of the LFO

Technically it has to be better.  The tricky part is actually adjusting it in circuit so it *is* better.   Suppose you match JFET to Vp +/-50mV, you would have to adjust the trimpots in the adjustable version at least that close.

[gaussmarkov]

>one is guaranteeing that no single resistance quits changing over the entire cycle
of the LFO

Technically it has to be better.  The tricky part is actually adjusting it in circuit so it *is* better.   Suppose you match JFET to Vp +/-50mV, you would have to adjust the trimpots in the adjustable version at least that close.

thanks, george.  that's what i was thinking.