runoffgroove JFET Vp measurement mod

[gaussmarkov]

I have been learning about JFETs and accidentally came up with a very slight improvement to the runoffgroove method for measuring Vp, the pinch-off voltage (or Vgs(off)), for these components. This is really, really minor but I had fun discovering it and decided to post for that reason.  Here's a schematic from LTSpice showing the runoffgroove circuit and my proposed modification:

I am just changing the 1M resistor into a 10uF capacitor.  Here's a transient analysis of the difference in measured Vp for the two setups using the default N-JFET model in LTSpice which has a Vp of -2V:

The Vp for the runoffgroove circuit comes out at 1.86349V and the modded version is at 1.99V in 10 seconds.  So the capacitor gives a more accurate reading after waiting a moment for it to charge up.

Here's why the capacitor works better:  with a source resistor there has to be some current through the resistor and, therefore, through JFET to keep the voltage up.  So the circuit cannot reach pinch off.

On the other hand, the capacitor builds up a charge and just holds it.  Neat, eh?  It was doing this simulation that caused me to look for the modification.

But here's the rub:  it doesn't make much difference for measuring the Vp of popular N-JFETs we use.  So ... never mind if you are not interested in this sort of thing.  On the other hand, if you are interested, I have more to tell you.    I figured out how to tell from a datasheet how much error to expect.  My formula for the Vp from the source resistor is

where

where R is the value of the source resistor, V_p is the actual pinch-off voltage, I_dss is zero-gate-voltage drain current, and r_ds0 is the zero-gate-voltage small-signal drain-source resistance.  Data sheets usually include some or all of these numbers.  For a Fairchild J201, the datasheet says that V_p is somewhere between -0.3V and -1.5V and I_dss  is somewhere between 0.2mA and 1.0mA.  The smaller  b  is the worse the difference is so to be ultra conservative take the largest I_dss and the smallest V_p.  runoffgroove uses R=1M.  The formula says that higher values of R will give less error.  You might have a 10M for an amz-fx MOSFET booster.

For the worst case b, I calculate 0.00015 and for the expression multiplying V_p I get 98%.  So you will be off by 2% at worst. Big deal.  And if you are just looking for matches on V_p, it won't make any difference at all.  If you use that 10M resistor, you are down to less than 1% error.  You can bet the guys at runoffgroove know all this.  I would.

All the best, Paul

[mojo_hand]

Pretty cool!

Maybe the guys at runoffgroove didn't want to hear us whining about having to spend $30 for a 10 uF, 1% filmcap when a 3 cent, 1% resistor would work almost as well.

[gaussmarkov]

Pretty cool!

Maybe the guys at runoffgroove didn't want to hear us whining about having to spend $30 for a 10 uF, 1% filmcap when a 3 cent, 1% resistor would work almost as well.

nah, that's not it.    any cap will do so long as it charges up to at least -V_p without exceeding its voltage rating.  all the capacitance does is affect how long it takes to reach pinch-off. 

[mojo_hand]

nah, that's not it.    any cap will do so long as it charges up to at least -V_p without exceeding its voltage rating.  all the capacitance does is affect how long it takes to reach pinch-off. 

Ah. good point.  Even slight DC leakage through the cap would be tolerable.

Tried it out yet?

[gaussmarkov]

nah, that's not it.    any cap will do so long as it charges up to at least -V_p without exceeding its voltage rating.  all the capacitance does is affect how long it takes to reach pinch-off. 

Ah. good point.  Even slight DC leakage through the cap would be tolerable.

Tried it out yet?

no, i haven't.  but i want to do that and measure the I_dss as well.  i want to see how constant the ratio is.  George Giblet mentioned in another thread that r_ds0 is fairly constant within production batches. and then i am going to see how well the JFET formula works for predicting its operation as a VCR.  as i understand it, knowing Vp and Idss may make it possible to predict accurately the effective drain-source resistance from Vgs and Vds.  and if you keep Vds small, which phasers do, then you can ignore the Vds contribution and the gate-source voltage varies the resistance of what is otherwise a fixed (linear) resistor.

so my grand plan is to see whether measuring Vp in this way is sufficiently accurate to design out the need for JFET matching.  the relevant formula for an N-JFET is

r_ds = r_ds0/(1 - V_gs/V_p) = - V_p/{2*I_dss(1 - V_gs/V_p)}

where r_ds is the drain-source resistance that we want to control with the gate-source voltage V_gs.  for this to work, V_p < V_gs < 0 and for it to be accurate, V_ds needs to be an order of magnitude smaller than both of these.  from what little i have seen, it appears to me that phasers keep V_gs close to V_p and V_ds is hovering around zero, all this relative to the reference voltage.

so that in theory you only need to rescale V_gs for each JFET's gate.  maybe with the right LFO settings, that will be nothing more complicated than a resistive divider.  if r_ds0 is not stable enough, then i guess you will also need to tweak the bias of each JFET.  i doubt that you could just stick in a bunch of trimmers and dial everything in.  but maybe you can work out all the necessary values in advance with careful measurement and some calculation?  no manufacturer would have time (=money) for this but, hey, DIYers obviously do. 

your point about leakage is right on.  thanks for emphasizing that.  better to use a smaller nonpolarized film cap.  i imagine 100nF would work fine and it would be faster. 

thanks, paul

[gaussmarkov]

hi,

i tried this out and in the process discovered a logical error in what i said previously.  i miscalculated the worst case scenario.  i said,

For a Fairchild J201, the datasheet says that Vp is somewhere between -0.3V and -1.5V and Idss  is somewhere between 0.2mA and 1.0mA.  The smaller  b  is the worse the difference is so to be ultra conservative take the largest Idss and the smallest Vp.  runoffgroove uses R=1M.  The formula says that higher values of R will give less error.  You might have a 10M for an amz-fx MOSFET booster.

For the worst case b, I calculate 0.00015 and for the expression multiplying Vp I get 98%.  So you will be off by 2% at worst. Big deal.  And if you are just looking for matches on Vp, it won't make any difference at all.  If you use that 10M resistor, you are down to less than 1% error.

actually, larger  b  is bad.  so worst case from this datasheet data is  b = 1.5/(2*0.002*1,000,000) = 0.000375  and off by 2.7%.  not a big change, but i had the logic wrong.

i tried using a 100n box film cap and a 10M resistor.  runoffgroove suggests a 1M resistor, which will be off by more.  i set the measurement up on a breadboard and measured the 4 JFETs that happened to be on the breadboard for some other purpose that i have now forgotten.  two were TIs and the other manufacturer's logo i didn't recognize.  here's what i got,


      
         
         
         
         
         
         

	Vp		Idss mV	Idss mA	Rds0	B	Pred %	Obs %
JFET	100n cap	10M resistor
1	1.181	1.160	91.5	0.92	641.483	6.41E-005	0.99	0.98
2	1.184	1.164	93.8	0.94	627.343	6.27E-005	0.99	0.98
3	1.058	1.040	85.2	0.86	617.167	6.17E-005	0.99	0.98
4	1.056	1.039	85.5	0.86	613.839	6.14E-005	0.99	0.98

so the errors from using the resistor are a little bigger than what's predicted.  maybe my DMM is to blame.

post script:  let's see i should probably explain the table (which i posted prematurely--sorry--it was a mistype).  the first column labels the device under test.  the second column is the Vp measurement with the cap and the third the Vp with the 10M resistor.  the latter is always less than the former, as expected.  Idss mV  is the voltage reading for measuring Idss using the ROG circuit for this.  Idss mA is the Idss measured in mA.  Pred % is the predicted decrease due to the resistor.  Obs % is the actual percentage decrease observed in the two Vp measures on the left.

[George Giblet]

Jfet matching was discussed some time back in this thread:

http://www.diystompboxes.com/smfforum/index.php?topic=29513.0

Testing at low current is much better.  Replacing the 1M with 10M in the circuit you gave should be good enough.   Adding the cap is a good idea to help reduce problems with noise.  In practice placing the multimeter on the output terminal with put a 10Meg resistance across the cap - that's where you values will differ from the simulation.  As we see from time to time some people's multimeters have impedances less than the defacto 10M DMM input.  A buffer will help that, as per stm's ckt.

[gaussmarkov]

Jfet matching was discussed some time back in this thread:

http://www.diystompboxes.com/smfforum/index.php?topic=29513.0

Testing at low current is much better.  Replacing the 1M with 10M in the circuit you gave should be good enough.   Adding the cap is a good idea to help reduce problems with noise.  In practice placing the multimeter on the output terminal with put a 10Meg resistance across the cap - that's where you values will differ from the simulation.  As we see from time to time some people's multimeters have impedances less than the defacto 10M DMM input.  A buffer will help that, as per stm's ckt.

thanks, george.  although i am several years behind that curve, at least i am on the right track.    i really appreciate your help.  as you can see, i have managed to learn quite a bit working off your comments.

i guess i am confused by your comments, but i will ponder them.  my impression is that the cap clearly dominates any resistor and that this is validated by the higher Vp measures. 

going to a 1M resistor might improve the performance of the DMM reading but you obviously pay a price in more current leaking through the JFET and a lower reading.  i will give it a try.

[George Giblet]

>i guess i am confused by your comments, but i will ponder them.  my impression is that the cap clearly dominates any resistor and that this is validated by the higher Vp measures.

The effect of the cap is transient.  (Except where there are oscillators etc) The cap should be able to be pulled from a circuit and the *DC* conditions of the circuit are the same as if the cap wasn't there.  Real caps do leak but unless there is something wrong with them it is quite small. 

In your simulation you are seeing a transient, the output voltage will eventually reach a value close to the steady state value (at time = infinity).  You might have found you needed a cap because the simulator didn't like the source being unconnected,  the only way around this is to put in a large resistance to ground, say 100MEG or 1G ohm.  If you go too high numerical rounding will cause the simulator to do funny things - like not converge to a solution.

The cap should have no effect on the DC value.  In high impedance circuit you can get different measurements in practice because of noise, in this case a cap can help.  But as far as idealistic theory goes you shouldn't need it.

[gaussmarkov]

here are the Vp results for a 1M resistor: 1.089, 1.094, 0.985, 0.984.  unfortunately, these are much worse than predicted by the equations.  that is disappointing.  it suggests the equations don't work so well in the neighborhood of Vgs near Vp.  or that i made a mistake.  i wonder what the next order of approximation looks like.

as i said, for matching on Vp none of this matters unless Idss happens to be unusually out of line.  the Vp measures will order JFETs correctly and assign the same value to to JFETs with the same actual Vp if their Idss values also match.

[gaussmarkov]

>i guess i am confused by your comments, but i will ponder them.  my impression is that the cap clearly dominates any resistor and that this is validated by the higher Vp measures.

The effect of the cap is transient.  (Except where there are oscillators etc) The cap should be able to be pulled from a circuit and the *DC* conditions of the circuit are the same as if the cap wasn't there.  Real caps do leak but unless there is something wrong with them it is quite small. 

In your simulation you are seeing a transient, the output voltage will eventually reach a value close to the steady state value (at time = infinity).  You might have found you needed a cap because the simulator didn't like the source being unconnected,  the only way around this is to put in a large resistance to ground, say 100MEG or 1G ohm.  If you go too high numerical rounding will cause the simulator to do funny things - like not converge to a solution.

The cap should have no effect on the DC value.  In high impedance circuit you can get different measurements in practice because of noise, in this case a cap can help.  But as far as idealistic theory goes you shouldn't need it.

it sounds like there is a misunderstanding here.  the cap has a desireable effect on the voltage at the source and that's why it's a better choice than a resistor.  or put another way, the long-run steady state is exactly where we want to measure Vp.

consider what happens starting with an uncharged cap in the schematic i posted above.  both gate and source are at 0V.  with Vgs=0, current runs through the drain-source connection and this charges the cap.  as a result, Vgs starts to fall towards Vp.  it continues to do so as long as 0 > Vgs > Vp.  theoretically, it stops at time=infinity at Vp.  and it stays there.

LTSpice doesn't seem to need those kludge resistors.  it works fine without them.  i guess that is part of the friendly front-end that they put together.

[George Giblet]

I have seen derivations in text books which have many assumptions and they show a 3/2 law instead of the usual squared (n=2) law.

I've done some curve fitting in the low current region and end-up with a power law around n = 1.8.  If you choose different points you get different n's.  I also remember if you derive the parameters at reasonably low currents then try to use these at very low currents it still doesn't match - indicating that the n=1.8 (or whatever) still doesn't represent what is going on.

This type of thing is common for modelling, you have to derive a set of parameters which suit you region of interest.  A good example is MOSFETs the spice models are usually derived at high currents.  If you try to use these models at the low currents in effects they fail dismally!  There's zillions of academic papers where people try to model the fine grain behaviour of devices.  Usually things get very complicated - sometimes you need to know the structures inside the part!

[gaussmarkov]

I have seen derivations in text books which have many assumptions and they show a 3/2 law instead of the usual squared (n=2) law.

I've done some curve fitting in the low current region and end-up with a power law around n = 1.8.  If you choose different points you get different n's.  I also remember if you derive the parameters at reasonably low currents then try to use these at very low currents it still doesn't match - indicating that the n=1.8 (or whatever) still doesn't represent what is going on.

This type of thing is common for modelling, you have to derive a set of parameters which suit you region of interest.  A good example is MOSFETs the spice models are usually derived at high currents.  If you try to use these models at the low currents in effects they fail dismally!  There's zillions of academic papers where people try to model the fine grain behaviour of devices.  Usually things get very complicated - sometimes you need to know the structures inside the part!

ah well.  at least the equations that we have predicted the direction of the effect correctly.  if you lower the value of the source resistor, the measure of Vp falls and that's exactly what i just observed.  it just fell more than predicted. 

[George Giblet]

> theoretically, it stops at time=infinity at Vp.  and it stays there.

Sure.  I know where you are coming from here.  Arguably as soon as you connect the meter the JFET will pass a low current and the value you read off will be as if the cap wasn't there.

[George Giblet]

> it just fell more than predicted.

Yes.  All the power laws have a similar shape it's just a matter of how much it bends up - there' no bumps.  Honestly I suspect the real answer will be more complicated than just playing around the power law's n value.


edit 1: For the record, I'm not actually sure what the measurement and curve fitting conditions were when I got my n=1.8 value.    I remember fitting  under all sort of cases: Idss fixed at the value measured with vgs=0, Idss allowed to vary, low currents, low and high currents, probably some others - all sorts of cases.

edit 2:  What I did to get n=1.8:  I measured Idss with vgs=0 at a suitably high Vds voltage.  I then measured vgs at two points, one to get Idss/10 and one to get Idss/60.  If I forced Idss to be the value measured at vgs=0, then fitted the parameters Vp and power law n,  I got an n=1.8.   However, if I let Idss vary I ended up with an n closer to 2 ie. the square law.   The IDSS value ends up being higher and the Vp values aren't much different to the forced Idss case.  The initial reason for forcing Idss is that the model should pass through that Idss at vgs regardless of the power law used and we know it goes through that point because it is measured.

What that says is the n=2 model seems to be close at low currents.

Regarding the varying and fixed Idss:  What I think is going on is the higher varying Idss might be the correct value.  When the gate is tied  to the source there is an internal (ohmic)  voltage drop between the source pin and the real source point inside the JFET, in effect like sticking a parasitic resistor in series with the source.  Because Idss is measured at high currents the voltage drop across that resistance is going to be relatively high so it has maximum effect.   If you image setting Vgs = a small value corresponding to the resistor drop and, Idss = the larger curve fit value, then you can see that the drain current will less than the fitted Idss and more like the measured one.  So it seems Idss shouldn't be extracted at Vp=0 unless some allowance for an internal source resistance is made.   Some *rough* calculations shows the internal resistance required is about 22ohms, that seems pretty reasonable.  I'm just thinking out allowed here.

[gaussmarkov]

> theoretically, it stops at time=infinity at Vp.  and it stays there.

Sure.  I know where you are coming from here.  Arguably as soon as you connect the meter the JFET will pass a low current and the value you read off will be as if the cap wasn't there.

and the same effect is present if you use a resistor, right?  all i am saying is that other things equal the capacitor seems to be the better choice and a test of that is what gives you the highest measured voltage.  you cannot get a voltage higher than Vp.

observing the curve like you did is exactly what i planned to do.  thanks for explaining what you did and found.  for actual JFETs, the Ids/Vgs curves in datasheets and for some JFET SPICE models show increasing current even after the corner.  so i wonder if measuring Vp and then measuring current at Vds=-Vp, Vgs=0 would produce n=2 behaviour?  maybe a "suitably high" voltage is not such a good choice?

[George Giblet]

> nd the same effect is present if you use a resistor, right?

Yes, definitely.

> all i am saying is that other things equal the capacitor seems to be the better choice

It would seem so but I'm not sure how it will turn out in practice, leakage could keep charging the cap.  You have to connect something to measure the voltage.  Another way would be to use a bridge.

> you cannot get a voltage higher than Vp.
You can if leakage is present.  The cap voltage could creep-up slowly.

> so i wonder if measuring Vp and then measuring current at Vds=-Vp, Vgs=0 would produce n=2 behaviour?
From what I can see if you don't allow for the parasitic souce resistance it's not n=2 as a black box.

>maybe a "suitably high" voltage is not such a good choice?
The suitably high voltage thing tries to keep the JFET in the pinch off region, not the triode region where the equations change.

[gaussmarkov]

> you cannot get a voltage higher than Vp.
You can if leakage is present.  The cap voltage could creep-up slowly.

i was thinking of an unsigned value for V_p as in the voltage measured at the source in these circuits.  i don't think you can measure a voltage there higher than the magnitude of V_p, |V_p|.  V_p itself is negative.  V_p < V_gs < 0 for these circuits. 

just to be doubly sure that we are on the same page, i will describe my reasoning.

i think leakage can only lower the magnitude of the voltage at the source.  take the resistor case first with a current running through the JFET at just the right rate so that the voltage across the resistor is maintained at the V_gs that gives that current.  obviously this voltage has to be above V_p because no current flows if the voltage is below V_p.  if current somehow were a little higher then V_gs will fall (it's magnitude will rise) and that will cut off some current and move us back towards where we were.  if current falls a little below then the opposite happens and the higher V_gs will increase current again.  so the current and |V_gs| have a stable relationship, with V_gs always between V_p and 0V.

leakage in capacitors is like a resistor in parallel to an ideal capacitor and this has the same effect as the resistor by itself.  so either way, it seems to me that the measured voltage at the source is always going to be between 0 and |V_p|.  therefore, the method that gives the highest voltage reading is giving the most accurate one.  in my simulations and my actual measurements (with a box film cap) this is the method with the capacitor by itself.

> so i wonder if measuring Vp and then measuring current at Vds=-Vp, Vgs=0 would produce n=2 behaviour?
From what I can see if you don't allow for the parasitic souce resistance it's not n=2 as a black box.

just looking at some datasheets, i would say the curves are "obviously" not quadratic.  but quadratic may still be good enough as long as one doesn't expect to get the best parameters from these sorts of measurements of V_p and I_dss.

>maybe a "suitably high" voltage is not such a good choice?
The suitably high voltage thing tries to keep the JFET in the pinch off region, not the triode region where the equations change.

here's an example of the sorts of graphs that i was talking about. it's from the Vishay datasheet for a J201.

i've drawn in red two sorts of measurements.  the lower one corresponds the the current at the boundary of the ohmic and saturation regions, with V_gs=0.  this seems like the sensible place to get I_dss if there is any hope of obtaining parameters for a quadratic relationship.  the higher one corresponds to the sort of measurment that you describe.  V_ds is 9V and well into the saturation region.  for JFET behaviour like this, the notion of I_dsss as a a maximum current simply does not work.

[George Giblet]

Sorry for the late reply, it's been a busy week (and I almost forgot).

>  if current somehow were a little higher then Vgs will fall (it's magnitude will rise) and that will cut off some current and move us back towards where we were.

I'm not following you here. In your scenario you are assuming a resistor load across the cap?   If the current through the JFET is greater then the load resistor current then voltage on the source will keep rising up to towards the power rail.  There is no way the JFET can divert current to going because it is cut off (ie. |Vgs| is greater than |Vp|) - once you get in this region of operation the JFET has no control.  In practice, with a load resistor present, it is doubtful the leakage willl overcome the load.  Since the resistor load is present the JFET will conduct some current and the cap won't rise to the maximum and if you pull the cap the voltage will be unchanged.  My original statement was aimed at the case when there was just a cap.  If you put a current source, or resistor, across DS to simulate the leakage, your simulation will show Vs rising towards the supply

> i would say the curves are "obviously" not quadratic.  but quadratic may still be good enough as long as one doesn't expect to get the best parameters from these sorts of measurements of Vp and Idss.

Sometimes I think those curve can't be trusted to capture fine detail.  The early ones may even be hand drawn!

> here's an example of the sorts of graphs that i was talking about. it's from the Vishay datasheet for a J201.

Actually that's a very good point.

There is an effect in JFETs which isn't capture by the textbook equations.  It *IS* however capture in spice models (the parameter often called Lamda).  The effect is called channel length modulation which produces a postitive slope on the Id vs Vds curve, like your graphs.  And yes that's going to stuff up the measured Idss even if the voltage is suitable high.  There is a similar effect in transistors called the "Early Effect".  It's often a small effect typically you would have a 1/100kohm slope, but the J201 looks worse.   To account for this youneed to measure Id at two suitably high voltages which will let you extract Idss and Lamba.  If you want to extract the parasitic Rs as well you would need three points.  If you do a curve fit it should be able to fit all the data points and extract the parameters.  If you don't take your for points over wide enough range the parameters might not be physically correct.

The equations involving Lambda can be writting many ways by you essentially have to replace the normal Idss with  Idss*(1+Lambda*Vds).  As you can see from this equation as Vds gets larger the effective Idss (in the midset of the simple equations) gets larger, which produces the positive slope on the Idss vs Vds curve.

[gaussmarkov]

george, no worries about the delay.  i'm grateful that you are sticking with me through figuring this stuff out.

o.k.  i think i just realized a source of my confusion.  when you were talking about leakage you weren't referring to the capacitor.  you were talking about the JFET, right?  that would make sense of everything.  i was focussed on capacitor leakage, not knowing that JFETs have leakiage also.  having just looked at a datasheet, i see that it refers to a gate leakage current.  but i suppose that you're talking about drain-source leakage if the voltage can rise toward the supply.  so drain-source leakage with |Vgs|>|Vp| is a problem with some JFETs?
and thanks for the reference to lambda.  i actually figured that one out over the course of the week and it's nice to have a confirmation.

i'm building an adjustable power supply so that i can do some actual measurements and see how well i can reproduce these curves.  if that is successfull then i will give some thought to fitting the curves. you don't happen to have a reference on how to do that do you? 

also, i have gone ahead with designing an 4-stage phaser that might accomodate JFETs with different Vp values.  my strategy is to scale the LFO for each gate with an op-amp inverting amplifier.  the LFO is rigged so that it's output can be inverted, with the minimum and maximum voltages set to the desired ratio.  then a voltage divider brings that down to the scale appropriate for the JFET gates.  here's a part of the LTSpice sim for a single-supply version that i have been using for testing the idea:



the idea is that R17 and R8 would be chosen to compensate for different Vp values.  you wouldn't put trimmers in and try to dial those resistors in.  you would choose their values ahead of time based on measured Vp.   Vf would be chosen to get the right ratio for minimum and maximum LFO swings so that would be the "Depth" control.  the pot would scale the LFO into a reference 0 to |Vp| range.  any thoughts would be appreciated.  the simulations seem fine.

thanks a bunch, paul