Common Emitter BJT Calculations Driving Me Crazy!!!

[TELEFUNKON]

for FETs, I like the 2/3 concertina option

[alanlan]

Like I said, it's a very common mistake.  Try repeating your calculations with VCE set to half supply rather than VC.

That is an incredibly confusing way of saying:

Take the transistor completely out of the circuit and determine what the resulting voltage would be at the junction of the collector and emitter resistors, exactly as if they composed a basic voltage divider from the power supply to ground. The voltage that you calculate in this way determines the lower limit of the headroom range for that particular transistor stage (for those following along, this is roughly the voltage when the transistor is saturated, or all the way 'on'). Subtract this lower limit value from the total supply voltage, then divide that result by two: this determines the voltage you want to bias the collector at for the maximum amount of output swing.

See? Described, explained and instructed, without a single confusing mix of abbreviations and confusion over capital and lowercase letters. Just the simple why and how.

I only say this because if they are asking about how to bias a transistor, they obviously haven't yet gotten to the idea of steady vs. dynamic state response of an amplifier stage and have no need to know that nomenclature as it will only serve to confuse them.

It could be argued that VCE or VDS should be biased at a little higher than half supply.

Could it? Or are you actually doing so? If you are going to be publicly announcing that Jack Orman has made a 'common mistake' you sure ought to back that up with why, and you certainly should end with 'it could be argued'! He either made a mistake or he didn't.

If he did, prove it.

Which is it?

Like I said, try biasing the circuit so that the steady state voltage between the collector and the emitter i.e. VCE is about half supply rather than biasing so that the collector with respect to ground is 4.5V.  That way, it hardly matters what ratio of Rc to Re you choose, the transistor is always able to swing pretty much the same amount either way.

The reason I said that perhaps it should be biased so that VCE is say 5V rather than 4.5 is to account for the saturation region i.e. allow maximum clean headroom while avoiding the saturation region, but to be honest, if biased near half supply you've got it about right.

By the way, I see nothing wrong with trying to point out terms like VCE, Vce, vce, ID, Id etc. etc.  They're not confusing, they save on words.  It is easier to say VC than "the steady state collector voltage" is it not?  It is a common notation.  It has been made common for good reason.  And beginners can understand it if it is explained (as I attempted to do).  Read any basic book on transistor circuits and you'll see what I mean, including books for beginners.  Are you saying that demonstar isn't yet ready for this?  I think demonstar can make his own mind up.  You really should not criticise someone for trying to explain things, even if not to your own taste.

The reason I suggested trying to re-bias in a different way was to try to get the original poster (who evidently would like to understand what is going on a lot more) to go through the process and learn in doing so.

I feel no need to prove anything, but I'm happy to provide detailed explanations (as far as I understand things) if someone asks me to do so.

As for the MOSFET booster, it's pretty obvious once you understand the basic equations involved that it can't be biased at 4.5V and work very well.  This was one example of this common mistake having been made.  I suspect most people, in practice will build the circuit and tweak to their ears rather than assuming the DMM knows best.

[mac]

To be honest, I don't know where Re > Rc/2 is coming from.

John, I noticed this sometime ago while experimenting with Ge in a circuit I was designing for my personal use. I'm not saying that is a general rule but works ok "if base current is smaller than the divider current". I forgot to say this, sorry.

It could be useful to post the math of voltage divider and neg feedback networks, and when they are independent of hfe.

mac

[demonstar]

Like I said, try biasing the circuit so that the steady state voltage between the collector and the emitter i.e. VCE is about half supply rather than biasing so that the collector with respect to ground is 4.5V.  That way, it hardly matters what ratio of Rc to Re you choose, the transistor is always able to swing pretty much the same amount either way.

I'm not sure I understand this. How would this be any different to biasing the collector to ground at 4.5V (half VCC).

Re > Rc/2

I can't see how this can be true because this would mean the stage would have unity gain so no use as a amp. Yes stabillity is important but not if it prevents it functioning. I could well be misunderstanding but I can't see this myself. There are a lot of conflicting ideas surrounding this issue too by the looks of it.

I do know most of the letters. Vce etc. I just don't fully understand when to use capitals and when to lower case so curently when anyone other than me needs to undestand it I try to use words instead. Are capitals with capitals for DC readings? lowercase with lowercase for AC and lowercase with capitals for AC at a given snapshot in time? Or am i totally wrong?

Thanks!

[johngreene]

Like I said, try biasing the circuit so that the steady state voltage between the collector and the emitter i.e. VCE is about half supply rather than biasing so that the collector with respect to ground is 4.5V.  That way, it hardly matters what ratio of Rc to Re you choose, the transistor is always able to swing pretty much the same amount either way.

I'm not sure I understand this. How would this be any different to biasing the collector to ground at 4.5V (half VCC).

What he is saying is to have 1/2 the total voltage dropped across the collector to the emitter of the transistor. This would mean that if you have equal Collector and Emitter resistors, each one of them would drop 1/4 the total supply voltage.

Re > Rc/2

I can't see how this can be true because this would mean the stage would have unity gain so no use as a amp. Yes stabillity is important but not if it prevents it functioning. I could well be misunderstanding but I can't see this myself. There are a lot of conflicting ideas surrounding this issue too by the looks of it.

I think what Mac is saying is he observed this to be true with the Germanium Transistors he was using at the time. To me, this just means he has some really leaky transistors and that this 'rule of thumb' only applies to what he was doing at that time, with those transistors. So it other words, "Fahgeddaboutit".

--john

[Sir H C]

Look if Re is about  Rc/2 that sets your dc bias point and swing.  If you put a bypass cap across Re, you can get back your AC gain but still have a very stable dc bias point.

[alanlan]

Like I said, try biasing the circuit so that the steady state voltage between the collector and the emitter i.e. VCE is about half supply rather than biasing so that the collector with respect to ground is 4.5V.  That way, it hardly matters what ratio of Rc to Re you choose, the transistor is always able to swing pretty much the same amount either way.

I'm not sure I understand this. How would this be any different to biasing the collector to ground at 4.5V (half VCC).

Thanks!

OK, I'll try to explain with an example.

1) Let's say we want a simple gain stage of say nominally 5.

2) We may add a capacitor across Re to increase gain further than this and the maximum gain would be very much more dependent on hfe and other transistor parameters.  For this example I'm not going to worry about having such a capacitor as it simplifies the explanation.  There is no reason why you can't fit one though to increase the gain (and distortion) as it doesn't really alter the calculations here.

3) The first thing I choose is the collector resistor.  You may ask why.  This is because the value of the collector resistor largely determines the quiescent (i.e. steady state) collector current (IC - noting capital I and C for DC/steady state/quiescent conditions).  It also determines the output resistance of the gain stage which may or may not be an issue depending on what you are feeding next in your circuit.  i.e. if you are feeding a FET amplifier, chances are output impedance won't be an issue, whereas if you feed an inverting op-amp circuit with a 1K input resistor, then you will care about output resistance for two reasons:
  a) the effective gain will be reduced and
  b) the available output swing will be reduced.  I won't explain this in any more detail as it's probably another subject and I could go on for minutes.

Lets say we choose a value Rc = 20K.

4) Because we know that the gain of this stage is roughly Rc/Re, we can now calculate Re.

Re = Rc/gain which in this example is 20K/5 = 4K.

5) OK, so now we know Rc, Re and gain.  How do I set the bias?

What I want to achieve here is to have the transistor's VCE (i.e. voltage across the collector-emitter at steady state) about half the supply rail.  Why?  Because then it can swing roughly half supply in each direction!  Simple as that.  Maximum headroom.

So, if VCE = 4.5V assuming a nice steady 9V supply, there MUST be 4.5V in total across Rc and Re.  i.e. if you measure the voltage across Rc and the voltage across Re and add them together, then you MUST get 4.5V.  4.5V + 4.5V = 9V right?
(Here I assume that the collector and emitter currents IC and IE respectively are roughly equal which they will be for a transistor with decent Hfe).

So IE = more or less IC.

We can now calculate IC and IE as 4.5V / (Rc + Re). = 4.5 / ( 20K + 4K ) = 187.5uA

VE i.e. DC emitter voltage w.r.t. GND will be Re * IE (simple ohms law).

So in this example, VE = 4K * 4.5 / ( 20K + 4K ) = 0.75V.
And VC will be 9V - 20K * 4.5 / ( 20K + 4K ) = 5.25V.
VCE = 5.25 - 0.75V = 4.5V - bingo!
==================================

Now we know VE we can set our VB bias to roughly 0.75V + 0.6V (base to emitter voltage drop) = 1.35V.  So you would set up a voltage divider to provide about 1.35V at the base.

6) So this works pretty much for any value of gain less than about 10 to 20.  Once you get to higher gains, things start to fall apart because lower values of Re result in less negative feedback Hfe and other parameters start to come more into the equation.  These factors are *always* there; it's just that they are lessened by negative feedback caused by larger values of Re.  This really is getting into other territory.

Any questions please ask.

[R.G.]

Any questions please ask.

I prefer to start with the voltage division between Vce, Rc and Re and work backwards from there.  It amounts to the same thing because since the base current is small enough to ignore, the collector and emitter currents will be the same, therefore the ratio of the voltages across Rc and Re set the gain just as accurately as do the resistors themselves. You then choose the stage output impedance and current level at the same time; you pick either Rc or Ic, and the other falls out by ohm's law.

As you mention, the AC loading on the collector must either be greater than about 10x the collector resistor or must be taken into account in computing gain, as it reduces gain by lowering the AC load compared to the DC loading on the collector. Interestingly, this makes the point that one can't accurately design a single transistor CE stage in isolation, as whatever it drives will affect its gain.

The discussion here is impairing one of the important insights into biasing and designing with BJTs - the fixed nature of Vbe and the ability to ignore Ib in biasing matters. In fact Ib is not zero, and Vbe is not really constant, but they are close enough to make designing a BJT stage a breeze compared to things like JFETs.

In a BJT, one simply has to determine where you want the emitter voltage to be and what currents to flow, then set Vb to one Vbe bigger than VE and you're done. For critical things, one has to compute the Shockley emitter resistor and take that into account, but that's trivial.

It's much simpler than the gate-source drop on a FET, especially a JFET where it can be volts and highly variable, not alway 0.5 to 0.7V.

[alanlan]

As you mention, the AC loading on the collector must either be greater than about 10x the collector resistor or must be taken into account in computing gain, as it reduces gain by lowering the AC load compared to the DC loading on the collector. Interestingly, this makes the point that one can't accurately design a single transistor CE stage in isolation, as whatever it drives will affect its gain.
It's much simpler than the gate-source drop on a FET, especially a JFET where it can be volts and highly variable, not alway 0.5 to 0.7V.

and not only gain but headroom.  If you load a single stage with a resistance equivalent to the output resistance of the stage then the headroom is halved i.e. it can only swing half as much even if you boost the input signal even further.  This is another one of those forgotten pitfalls of discrete design I guess.  As you pointed out, aiming for a 10X load to collector resistance is a good benchmark to avoid taking away from what you've earned in your calculations.

One of the main points I was trying to make is that often times, elements from op-amp design are (kind of) super-imposed onto discrete circuits - the 4.5V bias gripe of mine is just one common example.

[mac]

I think what Mac is saying is he observed this to be true with the Germanium Transistors he was using at the time. To me, this just means he has some really leaky transistors and that this 'rule of thumb' only applies to what he was doing at that time, with those transistors. So it other words, "Fahgeddaboutit".

Look if Re is about  Rc/2 that sets your dc bias point and swing.  If you put a bypass cap across Re, you can get back your AC gain but still have a very stable dc bias point.

In fact I was working with very low leaky old Toshiba Ge, hfe:50, leakage: < 20uA. I was looking a temperature stable bias network.
I used 10k at C, 5k pot at E, 100k from B to Vcc, 39k from B to Gnd. In the range hfe:(50,150) and leakage:(0.02ma, 0.2ma) readings went from 4.7v to 4.3v. aprox. I finger heated transistors and no big thermal runaway.

mac

[demonstar]

Right guys, here it is now...

"http://www.aronnelson.com/gallery/main.php/v/Demonstars-Gallery/circuit+3.jpg.html"

It's now biased so that VCE is about 4.5V rather than in terms of Rc to ground. I have fiddled around with that on LTspice and it does provide a way better swing. I don't understand why it works but I'm able to implement it and make it work. So I'm happy for now! 

I understand how the load that is being driven affects the gain and moddeled it in LTspice to get a clearer image. (The article at GEO on impedance helped!)

I'm curious to know how bypassing Re works? I understand roughly but how do the calculations surrounding it work please?

Once I've learnt that I think I'm where I'd like to be for Common Emitter configurations and feel confident enought to be able to calculate one to to the job I want it to do (or near enough anyway) or to tweak an existing one).

Any suggestions on what I could maybe learn next? Other BJT configurations? FETs?

My college physics teacher has loaned me a book and it has a small section for electronics and it's got calculation questions in it surrounding common emiiter BJT configuration so I'm going to have a go at them to consoldate my knowledge I think.

Thanks! 

[PerroGrande]

Hi Demonstar,

Looks good.  Another thing to consider (as if there isn't enough already!) is the effect of the base biasing circuit on the input impedance of your stage.  Your 23K biasing resistor is going to dominate the input impedance of this stage.  This may or may not be an issue, depending on what comes before it.  If you have a higher Hfe transistor, you can get away with a less "stiff" voltage divider on the base and enjoy a higher input impedance.  Bootstrapping the stage is another way to solve the issue of input impedance.

But I'm straying away from your question... 

Bypassing the emitter resistor involves placing a capacitor (typically of large value) in parallel with the emitter resistor.  The capacitor will be a non-factor at DC, so your already well-designed biasing will be preserved.   However, as frequency increases, the impedance of the capacitor drops (1/2*pi*f*C).  In effect, the capacitor at signal frequencies (not at DC!) "looks" like the emitter resistance (well, in parallel with the real emitter resistor).

What does this do?  It allows us to build stages with larger gains without ridiculously small emitter resistor values (and the issues associated therewith) or large collector resistors (and the issues associated therewith).   To see the effect in action, try putting a 47uF capacitor in parallel with your emitter resistor and compare the gain (give it something like a 10mV signal at 1KHz in LTSpice).  To control the maximum gain at signal frequencies, you can place a resistor in series with the capacitor.

What bypassing the emitter resistor does NOT do is give you something for nothing.  You still have to build a stable DC-biased amp, and the limits of maximum swing (as determined by the power supply and biasing network) will still be there.

[demonstar]

Ok thanks a lot John I'll try that out now and let you know how I get along. I was thinking of putting a buffer before the stage that i'm working on currently to provide a very high input impedance for the guitar to feed then a low output impedance from the buffer stage to this stage. That should work nice I hope. anyway I'll go and play with LTspice and your suggestions.

[demonstar]

http://www.aronnelson.com/gallery/main.php/v/Demonstars-Gallery/Circuit+4.jpg.html

I added an input buffer and bypassed Re to create a gain control. I have done some calculation and modelling and heres what i found... (All based on a 200k load.)

Frequency   Max gain   Min gain
100             29            10
1000           37            12
5000           38            13
10000         38            14

Just got to breadboard it and maybe some clippers but I'll see how it sounds. If I build it properly it'll probably need a pull down resistor too. I'm pretty sure this wouln't alter anything on the input side though. Anyway thanks to everyone who's helpped! I just wanted to show what is round about the final product of my work. Just slight tweaking and tidying up now I think. Like i say may add little bits. When it is COMPLETELY finished assuming it is any good, I'll post it in my gallery. Then there'll be one more booster style circuit spamming the web. 
I've learnt a lot making it though. Thankyou again.

So any advice on this...

Any suggestions on what I could maybe learn next? Other BJT configurations? FETs?

My college physics teacher has loaned me a book and it has a small section for electronics and it's got calculation questions in it surrounding common emiiter BJT configuration so I'm going to have a go at them to consoldate my knowledge I think.

[Faber]

So if I'm reading this correctly, you could have an inverting stage with a gain of 1 if Rc and Re are the same?

[R.G.]

Yes. Well, more correctly, you can have a single stage with a gain of BOTH +1 and -1 if the two are the same. It's been used since tube days, when it was called a split-load phase inverter.

[Faber]

Okay, I looked up phase inverters and that helps A LOT, but I have one more question.
Do you have to use both the + and - output on the inverter?

[johngreene]

Okay, I looked up phase inverters and that helps A LOT, but I have one more question.
Do you have to use both the + and - output on the inverter?

No. But if you are not going to use the inverting output you really don't need Rc there.

[Sir H C]

Yes. Well, more correctly, you can have a single stage with a gain of BOTH +1 and -1 if the two are the same. It's been used since tube days, when it was called a split-load phase inverter.

But as you, RG, well know, you have to have the load be very high or distort the weighting as the loading on the emitter side will work differently to the weighting on the collector side.

[alanlan]

Any suggestions on what I could maybe learn next? Other BJT configurations? FETs?

My college physics teacher has loaned me a book and it has a small section for electronics and it's got calculation questions in it surrounding common emiiter BJT configuration so I'm going to have a go at them to consoldate my knowledge I think.

http://www.diystompboxes.com/wiki/index.php?title=TechTips#Transistors