Quicky - input JFET buffer with good drive capabilities and adjustable DC level

[R.G.]

Here's one for the tinkerers.

1. Take an N-channel JFET. 2N5485 works well. Set it up with gate to ground through 1M, source to ground through 2K, drain to +9 through a 22K.
2. Take a 2N3906 or 2N4125 or 2N4250 or 2N5087 (you get the idea - low noise, high gain silicon PNP) and attach its emitter to +9 with a 100R, base to the drain of the JFET, and collector through 2K to the source of the JFET. Parallel the collector -to-source 2K with a 10uF cap, and take the output from the collector of the PNP. It will be something like 4-6Vdc. The output will have a gain of one from about 100mHz to 2MHz.

[Zben3129]

Heres a schematic for the buffer. I hope its right 




Zach

[B Tremblay]

Looks like there will be DC at the output, so a cap would be necessary.

[Zben3129]

It will be something like 4-6Vdc. The output will have a gain of one from about 100mHz to 2MHz.

This is meant to be the case.

If you needed to block dc from whatever you were connecting it to (next stage, opamp etc.) then yes a coupling cap would be needed.

Zach

[R.G.]

You're both right. Yes, there will be a DC voltage on the output. The DC is suitable as a bias voltage for other stuff in many cases. Or can be blocked with a suitable cap if not.

The voltage will vary with the JFET (big surprise there, eh?) but if you look at it, the source of the JFET sits wherever it would have anyway; the gain of the transistor converts the DC level up by the ratio of the two resistors to the source resistor; "gains" of other than 2 are possible by dinking the resistors. Voltage gain is also possible. The 10uF cap is there to hold the AC gain down to 1. If you remove it, you get an AC gain of about the DC gain. In this circuit, removing it gives a gain of about 2.

It's nice if you get JFETs with a natural bias voltage of about 4-5V because you can then make the collector to source resistor be zero and have a gain of one and full power supply voltage swing.

I was always frustrated with the operation of the self-biased JFET circuit. This little trick, which is not in itself new, cures some but not all of the self-biased JFET's ills.

[Gus]

Circuit like that is in a Gefell microphone I will look for a link to a schematic.

One can also set gain with circuits somewhat like that

http://www.national.com/an/AN/AN-32.pdf

I think I first saw some of the circuits in a radio shack reprint of a NS book around 1977.

[R.G.]

Yeah - there you go, on page 8. I knew it wasn't new, but I couldn't think of where I saw it. I should have thought of AN-32.

It's useful in a number of situations and it doesn't make the rounds much anymore. One of the nice things is that you can dink with the transistor and resistor values and get a whole slew of different characteristics.

[Gus]

I posted the link because there are other cool circuit fragments in AN-32. 

[R.G.]

I appreciate it. I was about to go dig out the Markus circuit collections to see if I could find it.

[Steben]

Could one make a 5-cent-garage opamp out of this? What if you tweak the value of the 2k-resistors? using a 10k "gain" pot for example with the center lug connected to the bypass cap?

[earthtonesaudio]

When I first saw this I immediately wondered how it compared to the "High impedance low capacitance amplifier" and "buffer" on page 8 of AN-32 (thanks for posting the link Gus).  I just happened to be trying to figure out that particular application at the time, coincidentally.

Looks like the main differences in R.G.'s circuit are the 22k on the drain, the 10uF capacitor/size of the feedback resistor, and the omission of the 1k pull-down on the collector.

My armchair analysis says that R.G.'s will get more gain from the JFET than the National appnote amplifier, but with that 10uF capacitor, it'll be reduced to almost one, due to the AC feedback of the PNP, and the PNP itself will have less gain.

In either case, the bulk of the output swing looks to be across the resistor-to-ground on the source of the JFET.  It appears that R.G.'s circuit will drive a little more AC current through that resistor, since the signal from the source of the JFET and the (in-phase) signal from the collector of the PNP both meet at the node of the two 2k's.  In the National appnote the signal from the collector is divided by the junction of the 10k and 1k resistors.  On the other hand, the National appnote looks like it has lower output impedance, so obviously I'm thoroughly confused.

I breadboarded the "amplifier" from the National app, and while it did give a little gain, it seemed to die if I changed any of the resistors.

Anyone care to share their understanding of this snippet?

[slideman82]

I always find that kind of configuration, the one with positive supply and a twisted PNP transistor at the output... what is the exactly advantage of this?

[Dragonfly]

I was playing around with a boost circuit thats not too far off from this a while back - i guess this thread is as good as any to post it for people to mess with...

Definitely not the "same" as you mentioned, but it does have nice high input impedance, low output impedance, and decent gain characteristics...uses a NPN in the second stage though...

[kurtlives]

^does it sound good with the second stage's base biased right to 4.5V?

[R.G.]

When I first saw this I immediately wondered how it compared to the "High impedance low capacitance amplifier" and "buffer" on page 8 of AN-32 (thanks for posting the link Gus).  I just happened to be trying to figure out that particular application at the time, coincidentally.

Looks like the main differences in R.G.'s circuit are the 22k on the drain, the 10uF capacitor/size of the feedback resistor, and the omission of the 1k pull-down on the collector.

My armchair analysis says that R.G.'s will get more gain from the JFET than the National appnote amplifier, but with that 10uF capacitor, it'll be reduced to almost one, due to the AC feedback of the PNP, and the PNP itself will have less gain.

In either case, the bulk of the output swing looks to be across the resistor-to-ground on the source of the JFET.  It appears that R.G.'s circuit will drive a little more AC current through that resistor, since the signal from the source of the JFET and the (in-phase) signal from the collector of the PNP both meet at the node of the two 2k's.  In the National appnote the signal from the collector is divided by the junction of the 10k and 1k resistors.  On the other hand, the National appnote looks like it has lower output impedance, so obviously I'm thoroughly confused.

I breadboarded the "amplifier" from the National app, and while it did give a little gain, it seemed to die if I changed any of the resistors.

It's a touchy little circuit. In general, you have to change both of the output side resistors to change things and keep it functioning.

I liked it because it cured some of the problems with a JFET source follower by adding more voltage gain (the PNP) and more current availability, hence a lower output impedance.

The key to it in my mind at least is thinking of the JFET as primarily a source follower. The source voltage on the JFET must be at whatever voltage it wants to be to keep the JFET happy and biased properly. With the gate of the JFET at ground, the source can and must be a few volts positive, but less than Vgsoff positive. The current that flows will be less than Idss but more than zero.

The PNP adds a lot of gain, and this needs some taming, hence the emitter resistor. The emitter will still be very near the power supply voltage at any current this runs, and so the base will be only a volt or so down from the power supply. The drain of the JFET will be at the same voltage; the resistor from drain to power supply helps control the JFET gain and the amount of current drive into the PNP.

The two resistors from the PNP collector to JFET source to ground control the overall voltage gain. Leave off the capacitor and the voltage gain of the whole mess is... what a surprise, 1+Rf/Ri. It's an opamp, of a kind. Rf is that resistor from the collector to the source; Ri is the resistor from source to ground. You're not quite as free to mess with the resistor values as you would be in a real opamp, as the voltage at the junction of the two resistors must be a good bias voltage for the JFET. That forces you to only low gains, because the DC voltage at the collector of the PNP is also multiplied by the 1+Rf/Ri gain, and you run out of power supply quickly on a 9V source.

In my case, this was fine, as I wanted only unity gain. So I had to remove the AC gain added by the Rf resistor; I did this with a BFC across it to make it a short at signal frequencies. There is a big hump in the response curve at frequencies BELOW the 1/2piRC turnover for this cap and resistor, which could be used for a bass boost if you made the cap smaller. I put the hump below audio with the 10uF.

Clearer? I've left a lot out that is secondary and tertiary to the main function. Ask where you're confused.

[earthtonesaudio]

Much clearer, thanks!  Also good to know I wasn't thoroughly confused.   

[slideman82]

I found a similar configuration at the end of the chorus preamp in the Roland JC120 schematic, it's similar, but not the same... do this make any difference?

[rnfr]

thanks for bumping this. i found it interesting.

[slideman82]

I've tried it a few hours agos, but with 24V dc supply, and it didn't work... with a 1M pot for bias, there where 22V on the drain, but it wasn's enough resistance... so, should I change something to make it work properly?

[R.G.]

I've tried it a few hours agos, but with 24V dc supply, and it didn't work... with a 1M pot for bias, there where 22V on the drain, but it wasn's enough resistance... so, should I change something to make it work properly?

It's not too forgiving of changing the power supply like that. Here are some things that may help understanding it.
The gate of the JFET is always at ground, of course. The source of the JFET will always be at less than Vgsoff, otherwise no current would be flowing (that's what Vgsoff makes happen) to pull up the source. So the source finds a voltage which lets the right current flow to let the right voltage happen... and it settles somewhere in there. A good guess would be something like half of Vgsoff.

As shown, the drain of the JFET will always be within about 1V of the power supply, because the base-emitter of the PNP is always about 0.5V, and with a small resistor in the emitter, the emitter does not pull down very far. a lot of current gets pulled through the PNP to pull the resistors up. The way to make the collector of the PNP come up to half the power supply is to increase the top output resistor in the ratio you want the output voltage to come up. If Vsource (=Vgs for the JFET) is maybe 2.5V, and you want the output voltage to be 12V, then you know the current in the lower resistor is 2.5V/2000 = 1.25ma. very near this same current flows in the upper resistor, so we want an upper resistor to be (12V-2.5V)/1.25ma = 7600 ohms; use a 7500. That will get you close. If you leave off the capacitor across the top resistor, the gain will be 7500/2000 = 3.75. If you put a cap across the top resistor, the gain will be very close to unity except that it will rise up to 3.75 again at DC where the cap can't short the gain setting resistor.