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matching JFETS

Started by Wounded Paw, December 02, 2008, 01:21:45 AM

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Wounded Paw

I'm planning to build a Phase 90 using the tonepad layout.  I have the 2N5952 fets but I need to match them.  Instead of putting together the JFET tester from GEO http://geofex.com/Article_Folders/fetmatch/fetmatch.gif can I use the test circuit included in the Fetzer valve article at Runoffgroove http://www.runoffgroove.com/fetzervalve.html
They are testing different but related values, the gate to source voltage for the GEO tester and the pinch-off voltage and saturation current for the ROG tester.  I'm asking because I already have the ROG Fetzer Valve tester put together.

mac

I'd use GEO, but there is another way of testing them by connecting fets as buffers, ie, D to Vcc, S to 10K to ground, G to 1M to ground, read voltage drop across the 10K.

If you want to verify that your fets are matched all the way perform GEO test using different values of Rset, ie, 1K, 10K and 22K.
Although unlikely, they could be matched at 10k but differ at 1K.

mac
mac@mac-pc:~$ sudo apt install ECC83 EL84

Ice-9

#2
I would use the R.G. Keen tester that has the op amp in it. If you want to measure the Idssas well as the Vp then put a spdt switch with the center pole (common) wired to the gate of the fet under test and one side of the switch to ground and the other to the output of the op amp.  I think this should work but i have not tested it.

Correct me if i'm wrong

after looking at this i don't think this mod will work as the Idss measuremnet will not work through the op amp. anyone else have any ideas on this ?
www.stanleyfx.co.uk

Sanity: doing the same thing over and over again and expecting the same result. Mick Taylor

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stm

#3
When matching JFETs for phaser use, your ultimate goal is having the gate-to-source cutoff voltages of the specimens as close as possible (this is usually referred to as VGSoff or VP).  Why?  Because the most interesting part of the phaser sweep occurs when the JFETs are near the cutoff region, and if not properly matched for VGSoff voltage, some JFETs will cutoff early and the phasing effect weakens.

Knowing the drain satruration currents (IDSS) or the specific channel resistances at a particular gate-to-source voltage is anecdotic for this purpose.

I recommend using ROG's JFET tester for its simplicity and because it addresses the main objective directly:  just focus on matching the VP (or VGSoff) parameter.

Cheers.

fogwolf

I have a question about RG's matcher - http://geofex.com/Article_Folders/fetmatch/fetmatch.gif

I'm not clear on where exactly the 2 DMM probes go. It looks like there's a feedback loop from the output of the op amp to the gate of the DUT. But there's also a line extending from this to the DMM. Does the arrow at the gate mean to measure with the meter there (and that there is a feedback loop as well)? Then the 2nd probe measures at the non-inverting input of the op amp? Then what is the "Vgs" with the arrow/ground symbol right next to the multimeter and between its probes exactly?

cpm

for the phase 90 transistors, do they all 4 need to be matched?
i think i read somewhere that 2 matched pairs were enough, no need for the whole 4-matched, it it true?

R.G.

#6
Quote from: fogwolf on December 03, 2008, 11:04:34 AM
I'm not clear on where exactly the 2 DMM probes go. It looks like there's a feedback loop from the output of the op amp to the gate of the DUT. But there's also a line extending from this to the DMM. Does the arrow at the gate mean to measure with the meter there (and that there is a feedback loop as well)? Then the 2nd probe measures at the non-inverting input of the op amp? Then what is the "Vgs" with the arrow/ground symbol right next to the multimeter and between its probes exactly?
Sorry for the cryptic schematic. To help you out, do this:
(1) On the drawing, erase the two lines that touch the DMM from the DMM leftward until they touch another wire.
(2) Likewise, erase the note "Vgs"  and the arrow pointing down.
(3) connect the DMM (+) lead to the output of the opamp
(4) connect the DMM (-) lead to the + input of the opamp
(5) read Vgs on the DMM display

No, there are not many feedback loops. The two lines to the DMM represent the DMM probes, but cryptically drawn.
The Vgs with an arrow is a way to indicate "Vgs is measured here".

Quote from: cpm on December 03, 2008, 11:38:49 AM
for the phase 90 transistors, do they all 4 need to be matched? i think i read somewhere that 2 matched pairs were enough, no need for the whole 4-matched, it it true?
It MAY be OK to use two different pairs if they are close enough. However, it is best if all four are as close as you can get. I believe that "no need for whole 4-matched" is incorrect. There definitely is a need for all four to be matched, but is not an absolute need. You can get some function with two pairs, and even with mild mismatches on all 4. But all four matched is probably going to work best.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

fogwolf

Thanks for the clarification RG. I've just about got it now - the only thing I'm still a little unclear on is what is the gate of the DUT connected to? The output of the TL072?

Quote from: R.G. on December 03, 2008, 11:52:10 AM
Quote from: fogwolf on December 03, 2008, 11:04:34 AM
I'm not clear on where exactly the 2 DMM probes go. It looks like there's a feedback loop from the output of the op amp to the gate of the DUT. But there's also a line extending from this to the DMM. Does the arrow at the gate mean to measure with the meter there (and that there is a feedback loop as well)? Then the 2nd probe measures at the non-inverting input of the op amp? Then what is the "Vgs" with the arrow/ground symbol right next to the multimeter and between its probes exactly?
Sorry for the cryptic schematic. To help you out, do this:
(1) On the drawing, erase the two lines that touch the DMM from the DMM leftward until they touch another wire.
(2) Likewise, erase the note "Vgs"  and the arrow pointing down.
(3) connect the DMM (+) lead to the output of the opamp
(4) connect the DMM (-) lead to the + input of the opamp
(5) read Vgs on the DMM display

No, there are not many feedback loops. The two lines to the DMM represent the DMM probes, but cryptically drawn.
The Vgs with an arrow is a way to indicate "Vgs is measured here".

Quote from: cpm on December 03, 2008, 11:38:49 AM
for the phase 90 transistors, do they all 4 need to be matched? i think i read somewhere that 2 matched pairs were enough, no need for the whole 4-matched, it it true?
It MAY be OK to use two different pairs if they are close enough. However, it is best if all four are as close as you can get. I believe that "no need for whole 4-matched" is incorrect. There definitely is a need for all four to be matched, but is not an absolute need. You can get some function with two pairs, and even with mild mismatches on all 4. But all four matched is probably going to work best.

R.G.

Quote from: fogwolf on December 03, 2008, 11:59:44 AM
Thanks for the clarification RG. I've just about got it now - the only thing I'm still a little unclear on is what is the gate of the DUT connected to? The output of the TL072?
Yes. The opamp's part in this is to sense the difference between the voltage divider and the source voltage and then to drive the gate of the JFET until the reference voltage and source voltages are the same.

Actually it's to drive the JFET and the meter. The meter, high impedance as it is, would load down the very-high-impedance JFET gate. The opamp takes care of setting the source and reference voltages to be the same, and also driving the meter, providing any current the meter needs without disturbing the JFET. No meter-induced errors. Or only the small ones.  :icon_biggrin:
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

fogwolf

Got it - thanks again!

Quote from: R.G. on December 03, 2008, 12:07:35 PM
Quote from: fogwolf on December 03, 2008, 11:59:44 AM
Thanks for the clarification RG. I've just about got it now - the only thing I'm still a little unclear on is what is the gate of the DUT connected to? The output of the TL072?
Yes. The opamp's part in this is to sense the difference between the voltage divider and the source voltage and then to drive the gate of the JFET until the reference voltage and source voltages are the same.

Actually it's to drive the JFET and the meter. The meter, high impedance as it is, would load down the very-high-impedance JFET gate. The opamp takes care of setting the source and reference voltages to be the same, and also driving the meter, providing any current the meter needs without disturbing the JFET. No meter-induced errors. Or only the small ones.  :icon_biggrin:

ballooneater

How close should the JFETs' VPs be to each other? Is + or - 0.01V good enough?

R.G.

I've used them matched to +/- 0.02 wth good results.

Maybe the right answer is to label all of your JFETs with a number and test them all, writing down the Vp next to the label number. Then sort the data in Excel or a table in word and look for groups. Pick the closest group of four. That's as good as you can do with the JFETs you have in hand.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

Zben3129

I took a giant piece of some kind of craft foam (don't use styrofoam, JFET's aren't to happy with static electricity), a black sharpie, and a boatload of transistors. Tested one, wrote its value on the foam, and stuck it in. When I got one with a repeat value I put it under the same place as the first one. I think I came out with 6 quads within .02 of each other. May have over transistor-purchased, now I have 5 matched sets just sitting around  :icon_eek: