Jfet biasing with balanced power supply

[shzmm]

Hello,

I have a question on how to bias Jfets with a balanced power supply, in this case +/-15V.  I am pretty clear on how to bias with a single supply, but those values obviously do not work when the source is not tied to the input ground.  Essentially, things should be the same in that the gate should be negative relative to the source.  However, finding the values for the Rs and Rd is giving me headaches.  I am using two MPF102s matched at around -3.1Vp and 9mA Idss.  My goal is to have around 20-25dB of total gain. 
The reason for using a balanced supply is that the circuit is acting as a preamplifier for a state variable filter (opamps) in a integrated bass preamplifier.
So, the question becomes is there a method to the madness of using Jfets in a balanced supply?   
thanks!

p.s. someone mentioned once a Fender Harvard schematic with Jfets that used a balanced supply, but the only one I could find was all opamp...

[SG6505]

I am not shure if this is a good solution but anyway, is it not easier to use half supply (+15V, gnd) only for the jfets? I assume you are going to have a DC-blocking capacitor after the jfet stages. Using +-15V is going to get a 30V source-drain voltage and the mpf102 is only rated for 25V max. Another way to go commonly used in stompboxes when using transistors and op-amps in the same circuit are to use single supply and biased input to the op-amps. But then you have to use 25V(+-12.5V) to not exeed mpf102 Vds rating. Just some thougts from a non expert.

[Ben N]

+1. I'm pretty sure I have seen it done that way, I just can't remember where.

[shzmm]

thanks for the reply.  i can see that as a solution, but i suppose i'd still like to figure out the mystery for myself. 
as for the mpf102 having a maximum voltage of 25, i assumed that meant measuring between the actual drain and source, not from V+ to ground.
but then i could be wrong, it wouldn't be the first time.  please let me know if i am incorrect.

[alanlan]

thanks for the reply.  i can see that as a solution, but i suppose i'd still like to figure out the mystery for myself. 
as for the mpf102 having a maximum voltage of 25, i assumed that meant measuring between the actual drain and source, not from V+ to ground.
but then i could be wrong, it wouldn't be the first time.  please let me know if i am incorrect.

Maximum device ratings always apply to the device itself, so if you can guarantee that the voltages on the device terminals can never exceed safe levels then you're OK.

As for the JFET stage itself, there are  a number of ways you can wire it.  Either use the +15V and 0V only (or the 0V and -15V), or connect the JFET circuit (i.e. Rd, JFET and Rs) across the rails ie. +15V to -15V.  The choice is really about how much you need the JFET output to swing and how much clean headroom you require.  As long as the output is AC coupled to the next stage, it doesn't matter too much, just make sure any polarised caps are connected in the right way around with respect to the DC conditions on either side.

Also of interest is how you bias the gate.  Given a bipolar supply, you can connect your circuit across +15 and 0V and then set-up a potential divider to bias the gate at a negative voltage so you don't lose much headroom across Rs.  In fact, you can even do away with Rs if you need maximum gain because it doesn't actually need Rs to bias with this method.  Same problems of JFET device to device variation still apply though and you will probably need some trim adjustment unless you use a more sophisticated biasing method.

[shzmm]

ok so that means using the negative 15V as a dedicated gate bias supply?  that would be good but it still leaves me with a limited output swing and headroom due to the 15V rather than 30V supply?   
at the risk of making a complete ass of myself,  i would really like to know how to set up the circuit in ray marston's fet series pt.2.  there he mentions a basic jfet "offset-biasing" system whereby "results can be obtained by grounding the gate and taking the bottom of Rs to a large negative voltage."  this seems relatively easy to implement given my circumstances.  it is the circuit i thought of when i started this, but i just can't figure out how to calculate the Rd and Rs values.  i started with the assumption of having max 5ma of current (60% of Idss) for both gain stages which i calculate means 6k (30V/.005mA) of total resistance.  unfortunately, this didn't work for me unless the source goes to the negative supply. 
also, in the an102 biasing manual it talks about source follower circuits with source resistors on negative voltages as being "able to handle large positive and negative signals" as opposed to those which tie source resistors to ground that can only accept large positive and small negative signals.
so is all of this useful for my application?  well i would like to have a very clean amount of gain with lots of headroom.
(2 stages of gain and an output buffer.)  but really i think now it is more of a desire to figure out these designs.   

thanks again for your help

[alanlan]

Sounds like you need to take a step back and review the basics.  Have a read of this thread in the wiki and see if it helps.  There's a nice description of how to set up for the required bias current and voltage gain.

http://www.diystompboxes.com/smfforum/index.php?topic=57219.0

[alanlan]

A few points based on what you have said so far:
The MPF102 has a 25V max rating as you say, so it isn't really a good idea to tie it across both +/- 15V rails because if the device isn't conducting then it will have 30V across d-s terminals.  So, either you pick a different JFET, limit the supplies somehow or just use the 15V and 0V rails (which is what I would do because this is really a lot of potential headroom).

You mention input ground not being the point the source is tied to.  This should not matter since you will presumably AC couple the input signal to the gate which is already biased as required. 

You also say you want to use 2 stages of a limited gain and then a buffer.  OK, lets say you want 10dB per stage.  This sets the Rd to Rs ratio to about 3.  I'm assuming you don't want to use a bypass cap to produce lots of less controlled gain but you can do that anyway,  it doesn't really affect the biasing arrangement.

I did some calculations once to work out what values of resistor and IDQ (quiescent ID) for a given voltage gain.  This is the equation (I can post the derivation - it's not all that difficult to work out).

IDQ.Rs = VS = (V+ - VDSmin) / (2.(n+1))

where:
IDQ = quiescent DC value of ID
V+ = supply voltage assuming 0V is the lower rail
VDSmin = simply lower limit you want to impose on VDS to keep the signal in the linear constant current region of the device - you can set this to say 1V.
n = voltage gain.

So, if you have V+ = 15V, VDSmin = 1V, and n = 3,

VS = 1.75V.

Now if you think about it, if VS = 1.75V then VD must be 3 times this value subtracted from the supply voltage (because Rd/Rs ratio has been fixed at 3).

VS = 1.75V and VD = 9.75V leaving VDS = 8V.  i.e. VDS can swing 7V down (to VDSmin) and 7V up to the rail.

This will give you the maximum possible voltage swing for the given amount of voltage gain.

Now all you have to do is determine IDQ which will in turn give you values for Rs and Rd.

IDQ depends on a number of factors, but primarily you should choose it to be able to deliver the maximum voltage swing into the load.  If the load is high impedance then IDQ can be quite low.  If you are following the stage with an emitter follower then the dominating input impedance is the transistor bias network, so use this as the load impedance.

A good way to look at the load is to ask your self how much AC current is required to drive it?  If you have a 14V swing into say a 100K load impedance then you need to be able to supply 140uApp.  So I would set IDQ to about 10X this i.e. 1.4mA or IDQ = 0.7mA.

This gives you Rs because from the above, Rs.IDQ = 1.75V so Rs = 2.5K and Rd therefore = 7.5K.

It is then just a matter of biasing the gate to provide IDQ = 0.7mA and Bob's Your Dad's Brother.

You can use the AN102 method for biasing - I know this works but it helps to draw bias lines on graphs and things and as I would find this hard to post, perhaps I can leave that up to you to work out.  If you need any extra help, shout.

[drk]

Sounds like you need to take a step back and review the basics.  Have a read of this thread in the wiki and see if it helps.  There's a nice description of how to set up for the required bias current and voltage gain.

http://www.diystompboxes.com/smfforum/index.php?topic=57219.0

nice topic, thanks for pointing it out alan

[shzmm]

hello again alanlan and thank you so much for helping me out with this.  i hope i didn't lose you here, but it took me a little while to sit down with all of this and try to stomach it...
ok, a few questions.  i follow your formulas and i really appreciate it as well-- exactly what i needed, something concrete!

IDQ depends on a number of factors, but primarily you should choose it to be able to deliver the maximum voltage swing into the load.  If the load is high impedance then IDQ can be quite low.  If you are following the stage with an emitter follower then the dominating input impedance is the transistor bias network, so use this as the load impedance.

A good way to look at the load is to ask your self how much AC current is required to drive it?  If you have a 14V swing into say a 100K load impedance then you need to be able to supply 140uApp.  So I would set IDQ to about 10X this i.e. 1.4mA or IDQ = 0.7mA.

what is the significance in making IDQ higher?  as this is from a transformer power supply (4A-- it's also running a small amplifier), i have more than enough current.  i originally came up with the figure of Idq from 60% of Idss because I read (somewhere) that if you follow the transconductance curve the line becomes more linear the closer to Idss it gets.
but no big deal, at least your reasoning is something i can work with i.e. using the following load to determine the necessary current.

the second thing would be the inevitable how to determine VGS?  from the datasheet for the MPF102:  .7mA ID and 8VDS intersect with a -2.5Vgs.  now that seems awfully close to the Vp of -2.9
for the devices i want to use.  would it then be better to skirt away from this region, i.e. increasing the Vgs to around -2?   making Id= 2.5mA.
thus Rs is 1.75/2.5= 700ohms and Rd is 2.1k.  how much does increasing current affect the temperature?  i assume it's going to get a whole lot hotter trying to push 2.5mA then .7mA.
i see on the charts 125 degree C for 5mA. 

ok one more question that i hope can clear up something for me.  input voltage.  say i have the gate biased at -2V does that mean a 1V input at Vp -2.9 will throw the fet into shutting off current?
i realize that 1V generally doesn't happen for more than a millisecond or two usually from a guitar, but the amp will be used with bass and keyboards.  so if i want to "design in" more headroom
i presume going with higher Vp units is better.  and/or, using a series input resistor - as discussed in the nice wiki you referenced. 

well i truly appreciate your sticking with me on this one.  i hope it helps someone else as much as it helps me.  really having a formula to use is so much nicer than making the sort of esoteric guesses that i've been stuck with so far. 

[alanlan]

what is the significance in making IDQ higher?  as this is from a transformer power supply (4A-- it's also running a small amplifier), i have more than enough current.  i originally came up with the figure of Idq from 60% of Idss because I read (somewhere) that if you follow the transconductance curve the line becomes more linear the closer to Idss it gets.

If you're running off a decent regulated power supply with loads of spare current then you can set a current as high as you like within the spec. as long as the device power dissipation is considered.  Yes the VGS/ID (transfer characteristic) is more linear away from the VGS(OFF) region, but as long as you are running with an unbypassed source resistor then vgs (the signal variation) will be quite small due to negative feedback provided by it.  The effect of this negative feedback is to linearise the amplifier.  If, on the other hand, you use a bypass cap across Rs then, yes, you will tend to get more distortion with it biased at lower currents with the bias point heading towards VGS(OFF).
Noise improves with increasing drain current and with lower resistance values in the circuit generally, but in the grand scheme of things, I doubt this would be a big problem.

the second thing would be the inevitable how to determine VGS?  from the datasheet for the MPF102:  .7mA ID and 8VDS intersect with a -2.5Vgs.  now that seems awfully close to the Vp of -2.9 for the devices i want to use.  would it then be better to skirt away from this region, i.e. increasing the Vgs to around -2?   making Id= 2.5mA.
thus Rs is 1.75/2.5= 700ohms and Rd is 2.1k. 
ok one more question that i hope can clear up something for me.  input voltage.  say i have the gate biased at -2V does that mean a 1V input at Vp -2.9 will throw the fet into shutting off current?
i realize that 1V generally doesn't happen for more than a millisecond or two usually from a guitar, but the amp will be used with bass and keyboards.  so if i want to "design in" more headroom

Again, negative feedback keeps vgs fairly small.  If you were to look at the signal voltage on the source, you will find that it follows the gate with a gain of somewhere near but not quite unity.  The higher Rs is, the more negative feedback you will get.  This amplifier is still a source follower even though we get extra gain on the drain.  If vg  = 1Vpp and Vs = say 0.95Vpp then vgs = 0.05Vpp.

The big problem is the variation in devices.  If this is a one off, then I would suggest connecting a trimmer across the +/-15V rails with resistors at each end to limit the adjustment range to say +2 to -8V, and bias the gate with this.  Then adjust the trimmer to get the IDQ you wish to achieve.  If you want this circuit to work with any MPF102, which is quite a tall order really with the 10:1 range of IDSS, then you need a more sophisticated approach.

how much does increasing current affect the temperature?  i assume it's going to get a whole lot hotter trying to push 2.5mA then .7mA.
i see on the charts 125 degree C for 5mA. 

Well it's power not current i.e. 2mA at 8V (assuming steady DC conditions) is 16mW - shouldn't get hot.