One-bit digital flanger/chorus/delay... is there a one-chip solution?

[oldschoolanalog]

Maybe something could be done with this?
http://www.spinsemi.com/products.html

[Thomeeque]

You are probably wrong here, R.G. (or are PT datasheets): clock frequency in PT series is not sampling frequency - sampling frequency is division of clock frequency and is much lower

Yes, I know that. I was hand waving to make the point that 64bit shift registers are not IMHO practical for a digital delay in a stompbox.

What's going on inside the PT series is that
(a) they are not using a first-order SD modulator, they're using at least a second or third order SD. That's so the signal-to-noise ratio gets better per amount of oversampling. Going to a higher order SD improves S/N by selectively moving much of the noise power up in frequency. This gets it further from the signal you're trying to get
(b) they *may* be using a PLL inside to multiply the clock for higher speed sampling; don't know this, but it would be a reasonable thing to do because
(c ) I'm pretty sure they run a digital low pass filter after the sampling to eliminate all that sampling noise that was moved to high frequencies by the higher order SD.
(d) I'm pretty sure they run a digital decimation process on the resulting filtered bitstream to eliminate all those extra bits once the noise is filtered out. This directly reduces the amount of bits they then have to store. It's the filtered, decimated bitstream that gets stored in the delay memory.

Doing all that work on the oversampled, filtered, decimated bitstream does reduce it back down to a bit density more like the minimum you'd need to put out decent sounding audio, since 128x oversampling is not needed for D-A to be good quality, only for the original sampling.

This is as I understand it. I've never actually built a sigma-delta modulator. But I'm a product of my environment, and I tend to believe textbooks. They've saved me a lot of work over the years.

Note to z, who's reading - yes, sometimes the textbooks are wrong - but mostly not. The race is not always to the swift, nor the contest to the strong, but that's the way to bet.

Oh, I'm speechless Thanks for explanation!

[R.G.]

Maybe something could be done with this?
http://www.spinsemi.com/products.html

Yep, it could.

[snap]

o.m.g., there`s a digital forum here? http://www.diystompboxes.com/smfforum/index.php?topic=50833.0 

[earthtonesaudio]

Maybe something could be done with this?
http://www.spinsemi.com/products.html

Well, I guess that answers the question posed by the subject heading.   
But now that I've seen it, it just doesn't seem as exciting when all the interesting parts are hidden inside.  I'm afraid that I have become enamored with the idea of using a small army of simple logic chips.  Like oskar said, there's just something poetic about it...

[R.G.]

Yeah, poetic. 

I once sketched out a design for an all-tube digital delay. Yes, digital.

Let's see: 44kHz sampling, one second delay, so 44kx16bits, one tube per bit, makes 704,000 dual triodes for the memory. Add 5% for logic, make it 739,200 tubes.

Heater power is 6.3V*0.3A*739,200 = 1.4 megawatts of heater power. With 150V for B+ and 1ma per tube standing current (only one half of each tube on at any one time) the plate power is 0.1MW, so total power required is 1.5MW. Typical power supplies are about 80% efficient if you don't try to regulate, so make that 1.9MW out of a very big wall socket. Since that all comes out as heat, you have to also REMOVE 1.9MW from the housings, so that's another 6% or so for SEER 20 air conditioning, so total of 2MW.

I decided I didn't have to figure out the weight... 

[Tantalum7]

Yeah, but how loud would the pop be when you clicked it on?

[earthtonesaudio]

Quad 64-bit space saver (surface mount): http://mouser.com/Search/ProductDetail.aspx?qs=sGAEpiMZZMtsbn1GaJysl%2fMNNke7pEsIbGMge8pIWPk%3d
Also, the 4517 is in stock, in DIP size.

[oskar]

Let's see: 44kHz sampling, one second delay, so 44kx16bits, one tube per bit, makes 704,000 dual triodes for the memory. Add 5% for logic, make it 739,200 tubes.

He, he... ENIAC was like ~17000 tubes. I wonder if it was ever used for music when the bosses weren't around...   

OK. How about a FIFO then? I'm not really sure what it is though but it said for serial data buffering.
http://se.mouser.com/Search/Refine.aspx?N=7103191+4294459457
Couldn't you do something with a FIFO with more than 1-bit width by just hooking the output from 1 line to the input of the next?

EDIT! He, he... welcome PK. I just beat you by 30 seconds by knowing a little less...   

[PK]

4517s are a little small...

...but there are many big shift registers out there.  They're generally called FIFOs (First In First Out) and you can find them in multiple flavors and densities.  The standard devices are generally parallel with 8 or 16 bits (or 9 or 18), but you can easily wire the bit 0 output to the bit 1 input and so on to chain the individual parallel strings into a single serial register (and provide taps!).

Looking at Digikey.... Ah... how about the IDT7204L12TPG.  It's pricey at $17.13 in single pieces for a 4K x 9 bit device, but consider the number of 4517s it would take to reach 36864 stages. With a 256KHz clock that would yield 144ms.  You could boost the sample rate generously here for a flanger since the required delay is so small. At the silly end of things, large modern devices yield densities like 128Kx36 (with a PBGA240 package ) which would give you 18 seconds at 256KHz.  I have also seen serial frame buffer chips for monitor scan rate converters with 2 million and 3 million stages and small packages.

A useful feature of the FIFO design is that you can clock data in and "fill" the buffer before you clock it out. If you reset the FIFO and then start feeding data in, the amount of time you wait before extracting it will become the length of the delay. In this way you can use the same chip for flange or delay, but you won't be using all of it for flange. With this architecture you'll need to convert your serial data to parallel before the FIFO and back to serial after the FIFO rather than just cascading the outs to the ins if you want to record a loop as you expand the delay length. Looping in digital is simple.

Asynchronous shift registers allow for some interesting circuits. By clocking the read and write operations separately you can induce time shifts or modulate the length of the register in a variety of ways.

There are multiple commercial effects using 1 bit delays with great success.

Cheers,
PK

[Cliff Schecht]

I'm surprised to see that more people haven't implemented FPGA's for this type of stuff.

[oskar]

I'm not really. When I see the 4517 chip I know instantly how to use it. An FPGA? I wouldn't know where to start really...
These FIFO registers seem sort of to be doing the right things but I don't know the amount of logic cirquits needed around them.
In my heart I'm still more excited by the quad 64-bit chip alex just posted.   

[earthtonesaudio]

Thanks for that post, PK!  Welcome to the forum.

I'm with Oskar in that I can easily understand how to make use of a shift register but the FIFO seems to be a bit more involved.
However, for the first time, I think I actually want to learn the tricks necessary to control a FIFO like PK suggested.  The lure of the Digital Side is strong...



[edit]R.G., do you have a vero layout for that tube thingy?   

[PK]

Thank you for the welcome, Oskar and Alex. 

There is a little more to using a FIFO than using a chain of 4517s, but the additions are small. If you look at the datasheet for the IDT7204 I mentioned above, you'll see the same function you see on the 4517... more or less. We'll just talk about using a single bit to keep it simple.

On the 4517 you send data to the data input and remove it from the data out. Same on the 7204.

On the 4517 you enable writes and clock the data in with a clock line. On the 7204, the write enable line is also the clock line so no difference in use there. The difference starts in that the FIFO also has a read clock where the 4517 always has 64 position shifted data available. If you tie the 7204 read and the write clocks together, you get action much like a 4517.

Now for the difference in use. At power-up, the FIFO needs a reset signal. This can be provided by a reset generator chip (3 leads and no worries), or by a simple RC circuit (10K from power to reset, 2.2uF from reset to ground, and a reverse biased 1N914 across the resistor). So far this is easy to satisfy. The datasheet says the FIFO must not receive clocking during the reset time so now we must add a logic gate to make sure the FIFO clock lines stay high while the reset line is low. OK, this is easy too. We can probably just use a NAND gate on the clock lines, fed by the clock and reset signals. This keeps the output high if either input is low, and while it will invert the clock, we probably don't care.

And now for the complex part. At this point you have a 1 bit deep FIFO. Not too useful. You need to send data in without removing it to fill the FIFO up. Most FIFOs have output signals which indicate if they are half or totally full. If you add a little more logic to the picture, you can use the totally full output to tell when you should start reading so that when full is indicated, you make a single bit of room in the FIFO with a read and then fill it back up with a write. It might be as simple as using a single 40xx chip to to this or maybe even simpler. Looking at the datasheet, it might just require using the /XO (expansion out) pin to clock the data out (/XO wired to /R).

Sequence:
Reset (no clocks active) --> Enable Writes to FIFO --> When FIFO indicates full, Enable Reads too

Thanks to the way the "full" logic works, you might need a two phase clock (using an inverted version of the write clock for the read clock) to keep things in sync. You could use one of the unused NAND gates as a clock inverter and that may complete the digital design.

The 7204 is part of a family including:

7203     2Kx9
7204     4Kx9       (144ms @ 256KHz)
7205     8Kx9
7206     16Kx9
7207     32Kx9
7208     64Kx9       (~2.3 seconds @ 256KHz)

Agreed... The lure of the Digital Side is strong...   

[slacker]

Great info PK, looks like this idea might be a goer, even if we are reinventing the digital wheel

Even better that quad 64-bit chip that Alex posted looks like it's just what I was looking for for my lunetta ideas.

[earthtonesaudio]

And now for the complex part. At this point you have a 1 bit deep FIFO. Not too useful. You need to send data in without removing it to fill the FIFO up. Most FIFOs have output signals which indicate if they are half or totally full. If you add a little more logic to the picture, you can use the totally full output to tell when you should start reading so that when full is indicated, you make a single bit of room in the FIFO with a read and then fill it back up with a write. It might be as simple as using a single 40xx chip to to this or maybe even simpler. Looking at the datasheet, it might just require using the /XO (expansion out) pin to clock the data out (/XO wired to /R).

So this is basically a super-long shift register, correct?

Thanks,
-Alex

[PK]

So this is basically a super-long shift register, correct?

Thanks,
-Alex

Yes, if you set it up to be.    The chip gives you multiple options.

Another way to make a small delay in a big FIFO is to use a CMOS counter such as a CD4040 to count out the number of stages you want to use: The FIFO reset is also used to reset the counter. The same clock feeds the FIFO write clock and the counter. The desired counter output (stage count) is used to enable the FIFO read clock.

Now you have three enable sources for the read clock:

(1) Small count output from CD4040 for Flanger
(2) Large count output from CD4040 for Chorus
(3) /XO or /FF (or /HF) output from FIFO for Delays

[slacker]

Thanks to the way the "full" logic works, you might need a two phase clock (using an inverted version of the write clock for the read clock) to keep things in sync.

If that is what's needed then you could probably use a CD4047 to provide the inverted clocks like in a number of analogue pedals like the ADA flanger or DMM.  Those designs also both allow modulation of the clock frequency. 

[earthtonesaudio]

Okay new idea (sigma-delta kicked my ass so I switched strategies):

Input>8-bit flash ADC>big FIFO>8-bit MDAC>Output.
(Clock is 4047)

Can anyone point me in the right direction for learning the details about hooking everything up, logic-wise.  PK's comments helped a lot, but I'm still sorta glazing over when it comes to what to do with which pin.

Bah! I'm starting a new thread in the digital forum.