One-bit digital flanger/chorus/delay... is there a one-chip solution?

[earthtonesaudio]

Is there something like a digital version of a BBD?  Meaning, something that can produce the same sorts of time delays that we like for flanger/chorus/delay pedals, but binary (one bit) instead of analog?

I have this idea to use a common counter, divider, or shift register type chip to implement a delay for a digital pulse train in the same way one would implement a delay for an analog signal.  Basically, you'd take your guitar input, convert to binary using pulse-width modulation (but with a very fast clock-near MHz frequency), then send the resulting high and low signals into a simple logic chip (or a few) to make a time delay.

I've been looking at Johnson counters, ripple counters, and stuff like that, and it seems like there just has to be something that will do this.

Fingers crossed... 

[oskar]

What you're looking for is a shift register. There are short shiftregisters in the 4000- series 8-bit, 64-bit and 128-bit. Then there is the 4006 chip that has up to 18 bit depending on how you connect it.

[oskar]

4006B 18-stage (4X4+2X1)
4014B 8-stage
4031B 64-stage
4517B 2X64-stage

How many stages/ delaytime do you want?

[slacker]

Neat idea. Like Oskar said I think shift registers are the way to go, spookily I was just looking at the 4517 datasheet as part of my current lunetta obsession. There's some good stuff in that forum, that you could probably use once you've got your pwmed signal.

At speeds of 1Mhz aren't you going to need quite a lot of stages/chips though?

[earthtonesaudio]

Thanks Oskar!  The 4517B looks the most promising out of all those.  More stages=

At speeds of 1Mhz aren't you going to need quite a lot of stages/chips though?

Hm... yes.  I was just thinking that the logic chip wouldn't play nice with a slow clock, but maybe a clock (min) of 40kHz is a better way to go.  (10kHz bandwidth with the "1 bit" PWM, but sample rate is divided by 2 at the shift register's output).

[oskar]

Hm... yes.  I was just thinking that the logic chip wouldn't play nice with a slow clock, but maybe a clock (min) of 40kHz is a better way to go.  (10kHz bandwidth with the "1 bit" PWM, but sample rate is divided by 2 at the shift register's output).

The 4000 series chips usually go over 1MHz all of them. But start with a slow clock and few stages and let the madness grow on you   
I experimented quite a lot with digital noise a couple of years ago and the funnies effect I came across was this.
Build a noise generator a la wasp and tap the noise at two points. at the first and last stages. Then pan these left/right and sweep the clock...  stereo noise...   recommended! Phasing and beyond!

[R.G.]

Congratulations. You're close to inventing either the delta modulator or the sigma-delta modulator/demodulator. I believe this was the train of thought that originally led to it being invented.

Yes, there are ICs which do this (sigma-delta) natively. The PT2395 and PT2399 are two of them. They both contain SD A/D/A and work natively on single bit streams. On the PT2395, you can even get at the single bit - it's what goes to the data in and data out pin of the memory chip.

However, the rules are a little different for bitstream A/D/A chips. In general, you have to sample bits faster to equal the resolution of a parallel A-D converter. So the length of the bitstream for a given length of audio is longer, and the frequency is higher.

Give a read:http://en.wikipedia.org/wiki/Sigma-delta and http://en.wikipedia.org/wiki/Analog-to-digital_converter

[Thomeeque]

I have based my flanger/chorus/delay project on PT2398 chip - this chip lets you tweak clock frequency (from ?? to 23MHz, same as PT2399) plus to choose one of 16 modes, where each mode sets one of few posible shift-register lengths (from 2Kbit to 20Kbit) and one of three possible clock to sampling frequency ratios (8, 16 and 32). Theoretical shortest delay time of this chip is 2048*8/23M = 0.712ms (f_s = 23MHz/8 = 2875kHz) - this would made already nice flanger (even not ultimate one), unfurtunately starting from f_s around 850kHz (~2.4ms) very strong noise is added to the output signal (f_s > 850kHz is probably too much for ADC/DACs) I have already stated this in separate thread while ago, I'm saying it here again to give you some idea of shift-register lengths and frequencies you will have to use and what you can maybe expect from PT2395 converters (could be similar to those inside PT2398). Plus maybe I will get some hints

T.

R.G.: Do you think there is some way how to tweak PT2398 to accept higher sampling frequencies? Eg. I have no idea what is circuitry around CC/GC pins (current control/gain control) about..

http://thmq.mysteria.cz/princezna/pt2398_datasheet.pdf
http://thmq.mysteria.cz/princezna/es56028_datasheet.pdf

[earthtonesaudio]

Using a PT23xx chip as an ADC for a short delay time seems brilliant yet disgusting.  I mean, you have a "real" delay chip just sitting there, twiddling its thumbs, while a weenie lo-fi shift register makes a puny short delay.  I'd think the PT23xx would get mad.

I'll probably just do this:

But start with a slow clock and few stages and let the madness grow on you

I think I'm gonna have to read the delta-sigma and ADC stuff about 31 times before it sinks in.  Thanks a lot R.G.  (  )

[R.G.]

I've never used the 2398, unfortunately.

However, if you want short delays, the PT2395 offers the choice of 256K and 64K memory chips to do its delay. I wonder what happens if you deliberately misuse it and pop in 16K or 4K memory chips, which use the same addressing and operational scheme...

[slacker]

Here's an interesting discussion that might be of some help http://www.electro-music.com/forum/viewtopic.php?t=23996

[earthtonesaudio]

D'oh!  The synth guys are already there!  Sometimes I wonder if coming from a guitar background puts me 50 years behind-the-times.

I do like the idea of doing it with simple logic chips.


I think this might be cool:
LFO/"manual voltage input" control a high frequency VCO.  HF-VCO output is used as the clock for the long string of serial shift registers, and also buffered, divided by 2, and used as the clock for the PWM/1-bit ADC.
(Dividing a master clock, rather than separate high-frequency clocks, should cut down on audible beat frequencies.)

I think that if you carefully picked the HF oscillator frequency and the number of shift stages, you could get some nice effects going on.  For example, if the master HF oscillator frequency dropped down to 40kHz at its lowest frequency, the PWM sample rate would then be 20kHz, and thus the audio bandwidth would be reduced to 10kHz, so there would be some high-end aliasing/bitcrushing going on, while at the same time the delay time is increasing to its maximum.  Sort of like how the PT2399-based delays get more dirty with longer repeats, but at a much shorter range of delays.

[R.G.]

I think that if you carefully picked the HF oscillator frequency and the number of shift stages, you could get some nice effects going on.  For example, if the master HF oscillator frequency dropped down to 40kHz at its lowest frequency, the PWM sample rate would then be 20kHz, and thus the audio bandwidth would be reduced to 10kHz, so there would be some high-end aliasing/bitcrushing going on, while at the same time the delay time is increasing to its maximum.  Sort of like how the PT2399-based delays get more dirty with longer repeats, but at a much shorter range of delays.

Why wouldn't you put a switched-cap input filter on it to drop the audio content down below 10khz when the main clock dropped so there wouldn't be aliasing? It would get duller, but not squarky.

[earthtonesaudio]

Why wouldn't you put a switched-cap input filter on it to drop the audio content down below 10khz when the main clock dropped so there wouldn't be aliasing? It would get duller, but not squarky.

If it turns out to be a "good sounding" flanger/chorus/whatever, then that's a great idea.  Filter more on the longer delays (which I believe produce notches lower in the audio spectrum) and pass the full bandwidth on the shorter delays (which produce higher-frequency notches).

On the other hand if it becomes clear that the device is more suited to "noisemaker" type of sounds, then you might want to keep the aliasing, or even exaggerate it.


Looking a little closer at the CD4517 chips, it would be a cinch to make a "through zero" type of circuit, by simply tapping one of the parallel outputs.  The true sicko would use a rotary switch to select different "zero" points.   



[edit] Here's a rough outline of what I'm talking about (Now that I see it, problems are jumping out at me!):

[R.G.]

I did some refreshing for myself, thought you'd like to see some of it.

If you're digitizing audio of a bandwidth of 20kHz, you need to sample it at more than twice the highest frequency in the signal to prevent aliasing. A sampling frequency of twice the highest frequency in the signal is called the Nyquist frequency, after the man who figured a lot of this out first. For full bandwidth audio, the CD folks picked 44kHz to be sure they were over twice the 20khz of normal human audio. Any less than that and you get aliasing. Fun, perhaps, but not fidelity by any means.

An analog BBD is theoretically an infinite resolution A to D. Its samples are not x or y bits wide, they're analog. And so all of the sampling-theory stuff works out almost perfectly. Well, there is the issue that the circuit itself adds analog noise as the BBD gets longer, each shift from one cell to the next adding some uncertainty. That's why the datasheets on BBDs talk about them being "low noise" as a virtue. But to get to 20kHz audio without aliasing, you need to sample with BBD at over 40kHz.

When you digitize into real digital words,  you want resolution to reduce quantization noise. Quantization noise in classical parallel A to D systems is 1.76 + N*6.02db per bit, where N is the number of bits. Each added bit give you 6db better signal to quantization noise. This is why CDs picked 16 bits  - you get a theoretical signal to noise ratio of close to 98db, and that's pretty darn good for any signal system. A quirk of sampling noise is that it's spread out over the whole sampling bandwidth from DC to Fs (sampling frequency).

Single-bit A to D is fundamentally 7.76db signal to noise. So sampling audio with a sigma delta and using about 40kHz to do it is ugly indeed. However, if you sample faster, the noise is spread out over a wider sampling bandwidth, and you get better signal to noise. Saving you a lot of math, you need a second or third order S-D modulator and about 128x oversampling to equal the performance of a 16bit parallel sampler at a given sampling frequency. So if you want to digitize audio with a S-D, you need to run your sampler at about 128*44kHz, or about 5.6MHz.

If you read the datasheets on the PT series, they have a basic clock of about 2MHz minimum. That means that either they are cutting back on the oversampling or get noisier, or both. But it's rock and roll, right, and we can cut back some. So let's say that for a single bit converter, we need to run it at 1MHz at least for acceptable sound quality, even to us.

You see where this is heading, right? If you have to sample at 1MHz, how long is a chorus? They're usually 20 to 30 mS.30mS divided by 1uS (the inverse of the sampling frequency) is 30,000 samples. So your shift register needs to be 30,000 stages long.

That's a lot... so, OK, we'll let the sound degrade some more, let more noise creep in, um... there must be something we can do.

The bottom line is that if you're making up digital delays out of 128 bit shift registers, you're going to have to buy a lot of them.

Of course, flangers only need something like 5 to 10mS of delay, so they're ... ah... only 5000 to 10,000 bits of memory long for a S-D.

This is the line of thinking that leads those PT echo chips to have 20k to 30K of onboard memory and the PT2395 to use a 64K or 256k memory chip.

[earthtonesaudio]

I figured, if clock speeds under 500kHz are okay for "consumer-fidelity" PWM amplifiers, then "guitar fidelity" can be slower still.
Basically I took the "average" guitar cab top frequency of 5-6kHz, and arbitrarily doubled it, calling 10kHz the absolute maximum for guitar.  20kHz sampling rate gives you one bit at 10kHz (if you're lucky), two bits at 5kHz, etc.  True, there will be audible aliasing, but maybe it's tolerable with some filtering, maybe not.  Rock 'n' Roll, right?

Anyway, if you used something like a LM566 as the master oscillator, you could clock from 40kHz up to 400kHz.  If you used 512 stages, that would produce something like 1 to 12ms delay time, plus some small propagation delay.

Then of course you'd have to filter or integrate the output to get your audio signal back, but you could do like the PWM amplifiers do, 2 pole L-C lowpass at the output.  I don't have much experience with it, but the relatively slow speeds used by amps already on the market is encouraging.

Bottom line, I'd be happy with something like this even if it had telephone fidelity.   

[oskar]

   Awh... I kind of liked the 4517 version... Although there is some sort of poetic beauty about a ~100 x CD4517 unit.

Whatever way you choose ( obviously a RAM... ), you need to sweep the delay somehow. I think the fastest TI CD4046 is some 20MHz maximum. And you can't run it too slow. Also I don't think you'll have the 20MHz available because the logic will need to go through enough maneuvers to need a few clockticks per read/write cycle. The rest of the unit could run off a much faster chrystal and then the VCO would just provide an interrupt for the read/write action. Should/could you alter both the length of the delay ( "distance between write and read place") and the VCO rate to get a good sweep range?

However, if you want short delays, the PT2395 offers the choice of 256K and 64K memory chips to do its delay. I wonder what happens if you deliberately misuse it and pop in 16K or 4K memory chips, which use the same addressing and operational scheme...

What kind of delaychips do commercial digital flangers use? Shouldn't there be equivalent chips like the PT2395?

Rock 'n' Roll, right?

Then of course you'd have to filter or integrate the output to get your audio signal back, but you could do like the PWM amplifiers do, 2 pole L-C lowpass at the output.  I don't have much experience with it, but the relatively slow speeds used by amps already on the market is encouraging.

I referenced elsewhere to a book by this guy Penfold who did a digital delay project and I don't think it had that fast delaytimes but I just hastily paged through it in a library once.

[Thomeeque]

If you read the datasheets on the PT series, they have a basic clock of about 2MHz minimum. That means that either they are cutting back on the oversampling or get noisier, or both. But it's rock and roll, right, and we can cut back some. So let's say that for a single bit converter, we need to run it at 1MHz at least for acceptable sound quality, even to us.

You are probably wrong here, R.G. (or are PT datasheets): clock frequency in PT series is not sampling frequency - sampling frequency is division of clock frequency and is much lower - e.g. PT2399: if size of memory is really 44Kbits and clock is set for 100ms delay (acceptable sound quality for sure), sampling frequency must be 44K/0.1 = 440Kbit/s only. One of versions of PT2399 datasheet contains delay time table - there is stated that e.g. for 4MHz clock you get 171ms delay - if we count f_s here, it's 44K/0.171=257Kbits/s, it's 16 times divided 4MHz. This ratio (f_s=f_clk/16) remains same for all values of that table. For PT2398 (ES56028) there is even clearly stated f_s for f_clk=4MHz (it's either 500 or 256 or 125kHz ~ f_clk/f_s ratios 8 or 16 or 32, depending on selected mode).

If this is true, and if it's true that PT2399 set for 300ms delay still produces acceptable sound quality, even 146kHz 1bit sampling is OK..

T.

[Thomeeque]

What kind of delaychips do commercial digital flangers use? Shouldn't there be equivalent chips like the PT2395?

Do commercial digital flangers use analog sweep (analogue LFO altering clock)? There are other ways how to flange digitally..

T.

[R.G.]

You are probably wrong here, R.G. (or are PT datasheets): clock frequency in PT series is not sampling frequency - sampling frequency is division of clock frequency and is much lower

Yes, I know that. I was hand waving to make the point that 64bit shift registers are not IMHO practical for a digital delay in a stompbox.

What's going on inside the PT series is that
(a) they are not using a first-order SD modulator, they're using at least a second or third order SD. That's so the signal-to-noise ratio gets better per amount of oversampling. Going to a higher order SD improves S/N by selectively moving much of the noise power up in frequency. This gets it further from the signal you're trying to get
(b) they *may* be using a PLL inside to multiply the clock for higher speed sampling; don't know this, but it would be a reasonable thing to do because
(c ) I'm pretty sure they run a digital low pass filter after the sampling to eliminate all that sampling noise that was moved to high frequencies by the higher order SD.
(d) I'm pretty sure they run a digital decimation process on the resulting filtered bitstream to eliminate all those extra bits once the noise is filtered out. This directly reduces the amount of bits they then have to store. It's the filtered, decimated bitstream that gets stored in the delay memory.

Doing all that work on the oversampled, filtered, decimated bitstream does reduce it back down to a bit density more like the minimum you'd need to put out decent sounding audio, since 128x oversampling is not needed for D-A to be good quality, only for the original sampling.

This is as I understand it. I've never actually built a sigma-delta modulator. But I'm a product of my environment, and I tend to believe textbooks. They've saved me a lot of work over the years.

Note to z, who's reading - yes, sometimes the textbooks are wrong - but mostly not. The race is not always to the swift, nor the contest to the strong, but that's the way to bet.