I need a buffer layout checked

sethyboy85 · February 24, 2009, 05:55:34 AM

<a href="http://s676.photobucket.com/albums/vv129/sethyboy/?action=view&current=fet.jpg" target="_blank"><img src="http://i676.photobucket.com/albums/vv129/sethyboy/fet.jpg" border="0" alt="Photobucket"></a>

It is my version of a buffer schematic, well I plan to change the 4.7k to a 3.3k or lower and my FET is 1. D, 2. S, 3.G and I have 1 on top. Output goes to a 50k linear blend pot and then to jack.
does this work or am I completely wrong?

GREEN FUZ · February 24, 2009, 06:07:58 AM

Have you based this on a known schematic? I can`t imagine it will work as the trace below the majority of the components hasn`t been broken, so the signal will just pass straight through. Not sure what`s going on with your ground line either.

sethyboy85 · February 24, 2009, 06:34:15 AM

yeah, first time using DIY layout.. haha

http://seanm.ca/stomp/minblend.html

sethyboy85 · February 24, 2009, 06:40:06 AM

http://i676.photobucket.com/albums/vv129/sethyboy/fet2.jpg
Since I will probably make a PCB for it.

my bad ground wire should be after the 4.7k not on the bottom.

GREEN FUZ · February 24, 2009, 07:31:50 AM

Alright were getting there

.

On the schematic R1 + R2 are ( I believe) the voltage divider so R2 needs to go to ground. You seem to have omitted it altogether.

C2 needs to come from source as does R3 which also goes to ground.

The easiest way to think about things when transferring a schematic to a layout is to literally copy it as closely as possible. Try laying out the components exactly as they are in the schematic.

sethyboy85 · February 24, 2009, 03:28:04 PM

doh! let me try to upload the right picture..

http://i676.photobucket.com/albums/vv129/sethyboy/fetv3.jpg

okay I have it flip flopped a tiny bit due to my FET I am using but essentially I copied the schematic straght up now.

GREEN FUZ · February 24, 2009, 03:48:19 PM

Quote from: sethyboy85 on February 24, 2009, 03:28:04 PM
...essentially I copied the schematic straght up now.

Are you sure? As an exercise try doing your layout exactly the same as the schematic. Note where C2 and the 3 resistors actually connect.

sethyboy85 · February 24, 2009, 04:42:04 PM

My DGS layout is different, schematic goes top to bottom D,G,S Mine- D, S, G,
so I flipped the middle part with the bottom and the bottom with the middle.

unless I am miss reading R3 in the schematic in relation to the FET?

R2 and R3 post "S" of fet?

GREEN FUZ · February 24, 2009, 05:06:57 PM

Quote from: sethyboy85 on February 24, 2009, 04:42:04 PM
My DGS layout is different, schematic goes top to bottom D,G,S Mine- D, S, G,
so I flipped the middle part with the bottom and the bottom with the middle.

Ahh! I see. Bit confusing.

Quote
R2 and R3 post "S" of fet?

If I understand you correctly, the answer is yes.

sethyboy85 · February 24, 2009, 05:09:22 PM

Thanks mate!

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I need a buffer layout checked