is it possible to switch a JFET directly from a PIC

[tempus]

Hey all;

Is it possible to switch a JFET on or off directly from the output of a PIC? Suppose the JFET were used for switching an effect in and out, so it would be biased at 1/2 V+ or about 4.5V. If I'm reading my data sheet right, the max supply voltage is 5.5V. Let's use 5V so that we don't stress the thing to its limits. The min output high voltage is V_DD-0.7 = 4.3V. Now looking at a data sheet for a J113, the max V_gs(off) is -3V. Here's where I'm unsure of my calculations. Since the drain and source are at 4.5V, hitting the gate with 4.3V wouldn't turn the JFET on would it? If not, are there other JFETs out there that could be switched from the output of a PIC?

Thanks

[R.G.]

The JFET doesn't care where the voltage comes from. As long as the voltage on the gate and channel are what it needs, it will switch.

The Vcc-0.7 is only under load for CMOS output uCs. If you put a mild pullup on the pin (some uCs have internal pullups programmable) it will probably pull to within a few millivolts of Vcc under very light loading. In either case, you'll put a diode in series with the uC pin to the JFET gate, so the pull down voltage is what really matters.

Bottom line, sure it works fine if you bias the channel up at about 5V, use the uC pin to pull the gate down to turn it off, and use a JFET with Vgsoff of less than 4.5V or so. Been doing it for years.

[tempus]

Thanks for that RG.

Bottom line, sure it works fine if you bias the channel up at about 5V, use the uC pin to pull the gate down to turn it off, and use a JFET with Vgsoff of less than 4.5V or so.

I think I'm missing something here. By channel do you mean the gate, or the drain and source? The JFET I've got here to experiement with is a MPF102, which I know is not ideal for this application. If I switch the circuit power off, the signal passes through. However, if I have the power on (which biases the drain and source up to 4.5V), I need to apply bias to the gate to make the JFET turn on (again passing the signal through), then I need a resistor to ground for it to turn off after the bias is removed. What is the diode for in your suggestion? Am I wiring this up wrong? Also, I've noticed on the 2N3819, the V_gs(off) is 8V, whereas the V_gs(off) for an MPF102 (and many other JFETs that I've been looking at) is -8V. Is this where I'm getting lost? Should I be using a JFET that has a positive V_gs(off)?

Thanks again

[R.G.]

I think I'm missing something here. By channel do you mean the gate, or the drain and source?

A JFET is really a two part device - the gate and the channel. The channel either conducts or it doesn't, depending on whether the gate squeezes it off or not. The drain and source are opposite ends of the channel. In many JFETs, drain and source are completely interchangeable. In fact, you have to do something funny in the making of a JFET to make them non-interchangeable.

The JFET I've got here to experiement with is a MPF102, which I know is not ideal for this application.

That's correct. You may never be able to turn it off. Actually, you can't tell. The datasheets I've found for the 102 say that Vgsoff is a maximum of -8V, and the minimum is unspecified. Strictly speaking, it may be as little as 0, not that you're ever likely to find one. But you can't be sure you turn it off unless you either test the one device in your hand, or else apply the -8V that is guaranteed to turn any of them off. See why datasheet reading is an art? 

If I switch the circuit power off, the signal passes through. However, if I have the power on (which biases the drain and source up to 4.5V), I need to apply bias to the gate to make the JFET turn on (again passing the signal through), then I need a resistor to ground for it to turn off after the bias is removed.

An MPF102 with the gate open, not connected at all, will conduct signal as though it was rdson. You make it conduct less by forcing the gate negative with respect to the channel. In your case, with the power off, the JFET gate (and everthing else) is sitting at 0V, so the JFET conducts. When you turn the power on, if the gate is open, it will still conduct, even if the source and drain are at some bias voltage. The channel resistance increases from Rdson towards infinity as you pull the gate lower than the channel. So something in your circuit is holding the gate down near ground. Notice that the "resistance" of the gate is the resistance of a reverse biased diode - many, many megohms, so "holding the gate down near ground" might be done by, say, a 10M resistor, or dirt on the circuit board even. The gate does not need a bias to make the JFET conduct. If by "apply bias to the gate to make the JFET turn on" you mean connecting it to the same voltage as the source and drain, yes, that's correct operation. What actually does is make the gate-to-channel voltage become zero, letting it conduct fully. When you "remove the bias", the gate capacitance stays charged to the former gate voltage, and may stay there for some time because you have removed the path for it to leak down when you opened the gate. JFETs are very, very, very high impedance devices. When you use a resistor to ground, you pull the charge off the gate capacitance, and force the gate to be negative with respect to the channel, turning the channel off.

What is the diode for in your suggestion?

It removes the possibility for you to muck things up by driving the gate positive with respect to the channel. If the gate voltage is near the channel voltage, the thing conducts. Pulling the gate even higher forward biases the gate-channel diode and injects your control signal into the channel. A series diode letting you pull the gate down only makes for more reliable operation.

Am I wiring this up wrong? Also, I've noticed on the 2N3819, the V_gs(off) is 8V, whereas the V_gs(off) for an MPF102 (and many other JFETs that I've been looking at) is -8V. Is this where I'm getting lost? Should I be using a JFET that has a positive V_gs(off)?

In this case, they have simply bee sloppy about the +/- signs. There do exist enhancement JFETs, but they're rarer than regular ones and not something you run into by accident.

You're probably doing it right, but the high impedances keep you from seeing that.

[tempus]

Thanks again RG for your informative answer.

A JFET is really a two part device - the gate and the channel. The channel either conducts or it doesn't, depending on whether the gate squeezes it off or not. The drain and source are opposite ends of the channel. In many JFETs, drain and source are completely interchangeable

OK, I knew that (score 1 for me!)

In this case, they have simply bee sloppy about the +/- signs. There do exist enhancement JFETs, but they're rarer than regular ones and not something you run into by accident.

And thanks for clarifying that. I was beginning to suspect as much, because every other JFET data sheet had a - sign in there, but it seemed like kind of a major error.

It removes the possibility for you to muck things up by driving the gate positive with respect to the channel. If the gate voltage is near the channel voltage, the thing conducts. Pulling the gate even higher forward biases the gate-channel diode and injects your control signal into the channel. A series diode letting you pull the gate down only makes for more reliable operation.

So if I'm understanding this, the idea is to have the gate biased so that the channel is on until you bring the channel to ground through the diode when you want to turn it off. This could be accomplished by connecting the gate (with the series diode) to, say, a PIC output, which could be programmed to stay high until you told it to go low, which would bring the gate to ground. Am I on the right track? I don't have a PIC here but I'm going to try to simulate this somehow to make sure I understand its operation properly. But if I have 4.5V bias on the channel (i.e., the drain and source) and none at all on the gate (so it's floating?) it should conduct, until I pull it to ground through the diode, right?

I'm going to read the rest of this over a bunch of times and do some experimenting until it sinks in before I trouble you with any more questions.

Thanks again

[R.G.]

So if I'm understanding this, the idea is to have the gate biased so that the channel is on until you bring the channel to ground through the diode when you want to turn it off. This could be accomplished by connecting the gate (with the series diode) to, say, a PIC output, which could be programmed to stay high until you told it to go low, which would bring the gate to ground. Am I on the right track?

Yes.

I don't have a PIC here but I'm going to try to simulate this somehow to make sure I understand its operation properly. But if I have 4.5V bias on the channel (i.e., the drain and source) and none at all on the gate (so it's floating?) it should conduct, until I pull it to ground through the diode, right?

Yes.