Phase 180 Plus (or Phase 90 for that matter) biasing question.

[frequencycentral]

I finished my build a week or so ago, and I'm just tinkering to get it perfect. The Vgs of the 2n5485 FETs I'm using is -1.8v. My vref is 4.1 volts. The vref voltage divider in the circuit consists of a 5.1 volt zener and a 10K resistor, I didn't include the 1n914 in parallel with the zener in my build as I assumed it was for polarity protection, which isn't an issue for me.

I've tried reducing the vref by paralleling a small value resistor with the zener, and I've found that a vref of 3 volts appears to be too low. So next I've tried raising to vref by paralleling a 1K resistor with the existing 10K resistor, this gives me a vref of 4.79 volts, which gives a better, deeper effect. I guess I can use a couple of 1n4148 in series with the zener to raise the vref instead of paralleling a 1K resistor with the existing 10K resistor.

I'm just wondering if anyone can give me a 'magic formula' for where I should aim for my vref to be based on the Vgs of the FETs I'm using? It seems to me that higher is better right now, I'm just wondering how high I should aim for. Thanks!

[frequencycentral]

Bump! Someone around here ,ust have experience of this..................

[Eb7+9]

I finished my build a week or so ago, and I'm just tinkering to get it perfect. The Vgs of the 2n5485 FETs I'm using is -1.8v. My vref is 4.1 volts. The vref voltage divider in the circuit consists of a 5.1 volt zener and a 10K resistor, I didn't include the 1n914 in parallel with the zener in my build as I assumed it was for polarity protection, which isn't an issue for me.

I'm just wondering if anyone can give me a 'magic formula' for where I should aim for my vref to be based on the Vgs of the FETs I'm using? It seems to me that higher is better right now, I'm just wondering how high I should aim for. Thanks!

yes there is ... review your jFET device theory (eg. Sedra & Smith) and consider that all the essential (characteristic) information about your device is contained in the numbers Idss and Vgs(off) @ a given test voltage - these are actually dependent functions but that's for another day ... the vgs numbers above were probably derived from the locally endorsed "matching" scheme which is well understood to be bogus by people who know their theory - do a goodle search ...

read the paper by Vishay on VCR applications of jFETs ... you'll notice that the VCR control range of a jFET device is 0 to Vgs(off) ... you want to bias your devices somewhere not too far from Vgs(off)/2, so that's why you need to know Vgs(off) for your devices - and that means doing it in a test circuit that has no or nealy no NFB ...

you want to match up devices that have similar Vgs(off) numbers so they have identical control ranges otherwise some devices will sway while others partly or not at all ... if you go one step further and match Idss so you have identical r(min) at Vgs=0 ... then you have what engineers refer to as matched jFET devices

if you want to build the ultimate phasor you should go the distance and find those two numbers for all your devices ...

I've tried reducing the vref by paralleling a small value resistor with the zener, and I've found that a vref of 3 volts appears to be too low. So next I've tried raising to vref by paralleling a 1K resistor with the existing 10K resistor, this gives me a vref of 4.79 volts, which gives a better, deeper effect. I guess I can use a couple of 1n4148 in series with the zener to raise the vref instead of paralleling a 1K resistor with the existing 10K resistor.

why isn't the bias control working for you ??

another approach takes advantage of the fact that all pass circuits act like constant gain circuits with that leg resistor/jFET taken out of the circuit ... that means that you can operate only one phasor stage (anywhere in the chain) with all the other stages disabled this way and still get the effect of one stage to filter through ... you can use a single stage to test out the bias response of all your devices (one at a time) to test and see which ones have a similar "kick-in" point ... this is a roundabout way of doing the matching without deriving dual coefficients for each device ...

what you do is run the oscillator at a fair speed to make you perception of effect depth easier and plop one device at a time in any one stage and turn your bias control until the effect is at its peak intensity wise and notice where on the trimmer is positioned for each device used in that one stage ... do the same with all your devices until you have enough that peak at the same location on the bias trimmer, and then use these throughout the phasor and adjust the bias trimmer at that position or thereabouts ...

of course this test will only roughly give you some level of coincidence ... it doesn't replace a full matching test but on average it's pretty useful for phasors - that's what I use ... this info is posted on my Phase-45 page

good luck

[frequencycentral]

Thanks for your response JC.

... the vgs numbers above were probably derived from the locally endorsed "matching" scheme which is well understood to be bogus by people who know their theory - do a goodle search ...

A tad inflamatory I feel.    The originator of that matching fixture has himself stated that it's not perfect, but will get people in the right ballpark at least. Which is a good thing.

another approach takes advantage of the fact that all pass circuits act like constant gain circuits with that leg resistor/jFET taken out of the circuit ... that means that you can operate only one phasor stage (anywhere in the chain) with all the other stages disabled this way and still get the effect of one stage to filter through ... you can use a single stage to test out the bias response of all your devices (one at a time) to test and see which ones have a similar "kick-in" point ... this is a roundabout way of doing the matching without deriving dual coefficients for each device ...

what you do is run the oscillator at a fair speed to make you perception of effect depth easier and plop one device at a time in any one stage and turn your bias control until the effect is at its peak intensity wise and notice where on the trimmer is positioned for each device used in that one stage ... do the same with all your devices until you have enough that peak at the same location on the bias trimmer, and then use these throughout the phasor and adjust the bias trimmer at that position or thereabouts ...

Yeah, I've done that, and am satisfied that my FETs are reasonably well matched.

why isn't the bias control working for you ??

The bias control does work, it just seems a little 'off', not centred like my P45 with JC mods build. And I think my notches are too high, maybe because the FETs have a Vgs of -1.8 volts, which I'm guessing is pretty high. I'd love some enlightenment on that.

I can build a circuit of this complexity, no problem, though I don't necessarily understand all it's electronic complexities. The key to the circuit being perfect seems to me to be the optimal Vgs of the FETs. So what would that be? I guess I'll just blindly stumble on and experiment with raising the vref with 1n4148s until I get it how I want it.

[Eb7+9]

A tad inflamatory I feel.    The originator of that matching fixture has himself stated that it's not perfect, but will get people in the right ballpark at least. Which is a good thing.

oh, don't cry - explain to me what's inflammatory about exposing a persistent source of ignorance ?

notice how none in this forum seems to really know how to play with the numbers every time an issue about jFETs pops up
Aaron brought this up recently ... just going 'round in circles - that's why, just maybe, academia/ieee/EDN/etc. do biz the way they do ...

if that test got people in the ball park then such questions as yours wouldn't keep popping up like they do
all this would have been answered in the first few years of this forum's existence if there wasn't the kind of mis-leading that goes on here

instead of relying on false expertise and arguing its limitations why not do some homework ?   
it's all there in the literature ...

[doc_drop]

instead of relying on false expertise and arguing its limitations why not do some homework ?   
it's all there in the literature

Wow, it must be hard to deal with such a pathetic group of ignoramuses.

But at least it is fun for you to post exposing their lack of education!

[frequencycentral]

JC, I'm just saying that I wouldn't be as close to well matched FETs as I am now without that matching fixture. But, yes I have to agree, the very fact that I'm not getting any answers that can pin down the answer to my question indicates that something is amiss somewhere.

I'd really like to get this build as close to perfect as I can without buying hundreds more FETs and becoming Professor Fetmatcher! So am I right in assuming my Vgs is a little high, and am I correct in thinking that the answer is increasing the vref?

[R.G.]

I finished my build a week or so ago, and I'm just tinkering to get it perfect. The Vgs of the 2n5485 FETs I'm using is -1.8v. My vref is 4.1 volts. The vref voltage divider in the circuit consists of a 5.1 volt zener and a 10K resistor, I didn't include the 1n914 in parallel with the zener in my build as I assumed it was for polarity protection, which isn't an issue for me.

I've tried reducing the vref by paralleling a small value resistor with the zener, and I've found that a vref of 3 volts appears to be too low. So next I've tried raising to vref by paralleling a 1K resistor with the existing 10K resistor, this gives me a vref of 4.79 volts, which gives a better, deeper effect. I guess I can use a couple of 1n4148 in series with the zener to raise the vref instead of paralleling a 1K resistor with the existing 10K resistor.

I'm just wondering if anyone can give me a 'magic formula' for where I should aim for my vref to be based on the Vgs of the FETs I'm using? It seems to me that higher is better right now, I'm just wondering how high I should aim for. Thanks!

You're chasing a misconception. This is what is leading to some of your frustrations as expressed below.

The relationship of Vref and Vgs in JFET phasers like this: Vref must be big enough so the LFO sweep from most negative to most positive does not exceed Vgsoff. They are not mathematically related any more that that, so there is no set of closed-form equations giving a single, magic value for Vref as a function of Vgsoff.  Vref just sets up the LFO sweep so that most of the JFET's Vgs range is covered by the sweep. You're missing the size of the LFO sweep entirely.

JC did get one grain of truth right: moving Vgs from 0 to Vgsoff changes r_ds from r_dson to substantially infinity for a JFET in isolation. In the P90 and its ilk, this means making the the gate Vref hold both source and drain just enough below the zener voltage for the whole range of the LFO voltage to fit inside it.

If the LFO sweep is bigger than enough to move the rds from rdson to infinity, there will be audible dead spots at the most positive and most negative parts of the LFO sweep where the JFET has already changed rds all it can, so even with the LFO changing, nothing audible happens. So the LFO peak to peak voltage must be less than Vgsoff. How much less depends on whether you want to sweep from many megohms to a few ohms, and whether your allpass filter does anything audible in those extremes of resistance.

Making the LFO voltage be the majority of Vgsoff from peak to peak means you can sweep the majority of the usable JFET resistance range, and making the LFO signal's DC level adjustable below Vref means you can move that usable range to the place in the JFET's resistance range where it does the most good audibly.

By trying different Vrefs, you're moving the LFO around with relationship to the static voltage of the source and drain, and also changing its size with relation to the LFO sweep, putting it at a level that moves the LFO sweep where it does more/less moving of the JFET resistance over an audibly useful range.  Don't confuse Vref with the critical relationship of the voltage the LFO puts on the gate with respect to the voltage. This last is what matters. Vref just makes the pool deep enough for the good stuff to happen. It's the voltage between gate and source that matters to the JFET.

I'm just wondering if anyone can give me a 'magic formula' for where I should aim for my vref to be based on the Vgs of the FETs I'm using? It seems to me that higher is better right now, I'm just wondering how high I should aim for.

yes there is ...

Unfortunately, there is not. Can you measure Vgsoff? Sure. Can you design an LFO for a certain swing? Sure. Can you calculate, from semiconductor physics where the Vgsoff of a JFET ought to lie? Sure. Can you buy JFETs like your calculations say?

Sadly, no. A little resorting to Occam's Razor give you that if you could, JFETs would not have been marginalized by the electronics industry. The industry has paid many smart people lots of money to figure this one out and come away empty handed. The advantages of JFETs are always crashed on the reality of high variability and unpredictability when the JFETs are not hidden inside some concealing feedback loop.

the vgs numbers above were probably derived from the locally endorsed "matching" scheme which is well understood to be bogus by people who know their theory - do a goodle search ...

JC, do you remember our last little talk about your practice of casting aspersions? Do you really want to get into that again?

you want to bias your devices somewhere not too far from Vgs(off)/2, so that's why you need to know Vgs(off) for your devices - and that means doing it in a test circuit that has no or nealy no NFB ...

Actually, no you don't. You want to bias your JFETs where the LFO voltage has room to sweep over the JFET's range of useful resistances. This may be at Vgsoff/2 if (1) the LFO voltage is precisely equal to Vgsoff from peak to peak and (2) what you want is a resistance range from rdson to infinity. You might want to bias it to sweep from 10K to 100K. Or 1K to 50K. Or even 20 ohms to 100Mohm. Those are all different solutions for both Vgs reference and LFO sweep. Oh, yeah, also different for each JFET.

you want to match up devices that have similar Vgs(off) numbers so they have identical control ranges otherwise some devices will sway while others partly or not at all ... if you go one step further and match Idss so you have identical r(min) at Vgs=0 ... then you have what engineers refer to as matched jFET devices

OK. The sun rises in the east every day and sets in the west. Perfectly matched JFETs are good. Motherhood is good. So is apple pie.

But 'splain to me then how the many hundreds of folks who have used the admittedly, up front imperfect, rule of thumb, rough and ready JFET matcher have come out with working phasers if a simple, rough and ready test didn't work. 

if you want to build the ultimate phasor you should go the distance and find those two numbers for all your devices ...

Actually, if you want to build the more-ultimate phaser, you'd curve-match them on a curve tracer or buy side-by-side dies from a wafer. There is always another step to be taken in the pursuit of perfection. To build the most-ultimate phaser (?) one could build up a set of four JFETs atom by atom with an electron-force stylus. Might take a while, though. 

another approach takes advantage of the fact that all pass circuits act like constant gain circuits with that leg resistor/jFET taken out of the circuit ... that means of course this test will only roughly give you some level of coincidence ... it doesn't replace a full matching test but on average it's pretty useful for phasors - that's what I use ... this info is posted on my Phase-45 page

Hmmm. You mean you want them to use a test that's only roughly good enough, not equation-solution perfect? JC, I'm ashamed at your inconsistency.

oh, don't cry - explain to me what's inflammatory about exposing a persistent source of ignorance ?

notice how none in this forum seems to really know how to play with the numbers every time an issue about jFETs pops up
Aaron brought this up recently ... just going 'round in circles - that's why, just maybe, academia/ieee/EDN/etc. do biz the way they do ...

if that test got people in the ball park then such questions as yours wouldn't keep popping up like they do
all this would have been answered in the first few years of this forum's existence if there wasn't the kind of mis-leading that goes on here

instead of relying on false expertise and arguing its limitations why not do some homework ?  
it's all there in the literature ...

JC, do you think that by just not typing my name that I won't have actionable grounds? I believe that your name calling has gone far enough. From the "Read this before you post" sticky:

I will consider direct attacks at other members as attacks to the forum. This type of posting with be dealt with harshly.

You have once again sunk to personal, direct attacks and I'm tired of it. Please append an apology here.