Building an Ibanez PT-909 Phazer

[cortey]

Hey everyone. I am attempting to build this pedal. However when i was breadboarding it, I came across the symbols CR1[No.1] and CR2[No.1]. it is unclear of what these are. if anyone could shed some light, much appreciated!

ibanez_pt909_phasetone.pdf (schematic)

[Mark Hammer]

If you look at any of the Boss or other schematics that also use a discrete flip-flop circuit for switching, you will see a small-value cap in parallel with a medium-value resistor.  Why Ibanez does not state values, I don't know.  Going by what seems typical for the rest of the values shown in the PT909 schematic, consider starting with 470pf in parallel with 100k.  That pair goes in each "CR" location.

[cortey]

ok thanks. didnt cross my mind to look at other circuits.. lol

[Mark Hammer]

Someone on another forum posted a query today about his SD-9 having distortion bleedthrough in bypass mode.  Having this thread and that other one co-occur today got me thinking.  I wonder if the reason the CR network is not specified in the many Ibanez schematics is because the "appropriate" values would depend on which batch/lot of switching FETs one happens to be dealing with.  In other words, the properties of any given switching FET might be optimized to go from fully on to fully off by means of those particular components.  I mean, it's not like the discrete flip-flop circuit is an industry secret, so why would Ibanez withhold that information unless they themselves couldn't say for certain what the values were.  Maybe there is some crucial information for us here.

So, does anyone who understands the workings of the discrete flip-flop have any comment to provide?  Am I on to something that would help to solve bleedthrough problems worldwide?

[cortey]

i dont know how those values correspond to the amount of bleedthru.

anyway i came across another issue while breadboarding my pedal. what way do pins on the transistors Q101-Q104 and Q105 go.
I found this: http://en.wikipedia.org/wiki/Common_gate

So this is what i have below, please correct me if i am wrong:
(the original full schematic is in my first post)

[Mark Hammer]

Type "2SK30A pdf" into your favourite search engine and look at the datasheet.

If the transistor is standing up on its legs and the flat side is facing yu, the pins poking out the bottom are numbered, from left to right, 1 - 2 - 3.  The schematic you linked to have the pinout S - G - D in positions 1, 2, and 3.

[cortey]

sorry, but you have mis-interpreted me.
The Red letters (DGS) on the pic i uploaded are not on the original schematic.
They are where i have them assigned to in my breadboard version.
i am asking if it is correct the way the red letters are as it is, or should SOURCE and DRAIN be switched?

any help is appreciated please 

[cortey]

does anyone know how to determine the proper orientation of the FET pins?

[Mark Hammer]

Generally speaking, when they are used as voltage-controlled resistors, drain and source are more or less interchangeable.

However, in this instance an RC network is added to the FET to raise the threshold of clipping.  I believe in this instance the network goes between drain and gate.