biasing question for JFET with bipolar supply?

[Sofl]

I am trying to understand how to correctly bias a JFET given a +/- 9v supply, in other words, a +9v supply for the drain and a -9v supply for the source (instead of having it go to ground).... aka a bipolar power supply.

Gee, I hope I phrased that correctly. *grin*


My understanding at this point is that  :   Vgg − Vss = Vgs + Id * Rs

So if Vgg = 0 then   :     Vgs + Id * Rs + Vss = 0

If I've chosen a JFET with a Vp of -1v and an Idss of 1 mA (a J201, perhaps) and I want to bias at 0.8 mA, then I would normally compute an Rs of 130 ohms (after being rounded to nearest common component value)....

:    Vgs = Vp ( 1 - sqrt ( Id/Idss )) = -0.104
:    Rs = 0.104 / 0.0008 =  130 ohms

But since I have a negative supply, then it seems that instead I have to increase Rs to compensate for the -9 Vss. In other words:

:   Vgg - Vss = Vgs + Id*Rs
:      0  -  -9  =  -0.104  +  0.0008 * Rs
:      8.896    =  0.0008 * Rs
:       11120  =  Rs

I would then round Rs to 11k.

I would then select an Rd of, say, 4500, end up with a drop of 3.6 volts, putting me right around 5.4 volts out, and a gain of approx -8.


So... am I doing this right? Is my equation to get Rs correct?


Thank you so very much in advance for any help you can give me!


Sofl

[PRR]

> since I have a negative supply, then it seems that instead I have to increase

If the "zero" point is -solid- (not some rail-splitter), then you may ignore the negative rail and just use one of the two 9V supplies the "usual" way.

However there is an advantage to taking the negative rail. You say you have a 1V 1mA JFET. I look in my bin and find 1V to 3V and a wide range of Idss.

For example, the JFET in my simulator is not much like yours. I had to use a value very different from 0.8mA and 130 ohms to get a "workable" stage with just 0V and +9V.



I have to re-figure or test every part. If I make a million, that's costly. If I don't trim, I probably get over 10:1 spread of current, so the drain resistor drop will be all over the place.

However if I string the source resistor down to -9V, as in the right version, then for all JFETs Vto= 1V to 3V, it will drop 10V to 12V, current is "FIXED" within 20%, drain resistor drop is set within 20%, and 4.5V to 5.5V at source is all the same to me.

The design at the left has a little voltage gain to drain; the design at the right has voltage gain less than unity. In most lo-Volt FET chores, you will have a large cap source to ground. Then the voltage gain is the same in both cases. (And for a specified bass corner, the long-resistor version can use a cap about 70% as big as the short-tail, not a big deal unless you buy millions of parts....)

> Idss of 1 mA ....and I want to bias at 0.8 mA

For best output swing you "usually" want to bias less than half the maximum current.

For maximum gain you bias hot and let the drain resistor take as much voltage as possible before the FET goes soft from lack of voltage. If you -know- your Idss, and are begging for gain, more-than-half is reasonable, but 0.8*Idss seems tight to me. Try it and see.

[R.G.]

Before you get too involved in calculating out a perfect bias point and parts, look at the datasheet for the minimums and maximums on the pertinent specs for Idss, Vgsoff, Vp, Yds, Rds, etc.

Idss is a maximum - under normal conditions the JFET will NEVER conduct more than IDSS. In fact, JFETs with source and gate shorted are selected for and used as constant current diodes.You can operate them with Vgs positive, but the gate starts conducting into the channel and you lose the advantage of the high gate impedance.

In normal operation, the source voltage will be higher than the gate voltage (using positive power supplies and N-channel FETs) How much higher depends on the other parameters of the JFET.

There is a reason (or more than one, possibly) that JFETs with their high input impedance and good frequency response have been left behind by the electronics industry.

[Sofl]

I chose those specific values ( 1 ma Idss, -1 v Vp ) just for proof of concept... I needed to know if I had a decent grasp of the math involved. I didn't want to start talking about device variations right off the bat, I figured it would just complicate things a bit. I can design around the device variations once I have a grasp of the basic concepts.

I looked up the datasheet to the 2n3819, ran my numbers, did the SPICE model, and my math lined up with it, so I think my question has been answered.

I did choose a higher Id for higher gain, absolutely- I intend to plug this into a distortion pedal, after all.  =)

I appreciate both of your inputs, you've given me the information I needed!


Sofl

[PRR]

> a grasp of the basic concepts.

I got distracted. If you take my right-side plan, but use your 4.5K drain load, aiming around 5.4V, then yes the part I show "6K8" would be 12K-15K, essentially your 11K (different due to different Vd goal and wider Vto assumption).

You got the math close enough to work.

> I didn't want to start talking about device variations right off the bat

True. But to get past second base you need to be aware of device tolerance. Stepping away from JFETs a moment: SPICE may tell you that a 2N2222 will bias-up at 1.000mA if you apply 0.6789V at base. Even if you could supply the 0.6789V bias, a real 2N2222 will sit almost anywhere except 1.000mA. Small changes in die area and doping will give significant change in current at a specific base voltage. Also temperature, though SPICE will model this trend quite prettily.

JFETs are a lot more stable once you get them biased OK. ("More stable" actually means lower gain, less reaction to change, which is a big reason JFETs {and vacuum tubes!} find few uses today.) However while a "2N2222" may need from 0.63V to 0.65V to pass 1mA, a box of same-number JFETs will spread over 1V to 3V, or even <1V to 8V for 1mA.

The "fix" affects circuit design. You use a emitter/source resistor "large" compared to expected device variation. BJTs of similar die-size are actually pretty consistent, so 1V drop is ample, and you can do less. JFETs vary more and have larger bias. In DIY it is practical to hand-trim each and every part, and even sort-out ones which don't trim nice. But is that the best use of your DIY time? Yes, if you do it once or thrice in private. If you want to build a lot of these circuits, or others want to build it, then hand-trimming is problematic.

In commercial designs where hand-trim is too costly, in circuits where idle current matters (in RF work it may not), you don't see the simple source resistor bias so much. Instead they bias-up the Gate to 5V or so (perhaps 5Meg+1Meg divider off a 30V rail), to swamp-out the Vto variations and get every part working at near-same current.

See how that affects design? Already you must add an input coupling cap, which you don't need when gate is DC grounded. You must judge how much voltage to put at the gate to swamp the Vto spread of the low-price wide-spread parts your purchasing manager may get (not that you can buy tight-spec parts yourself). And how much more on top for FET drop and drain swing. And if you can get such a high voltage in this modern low-volt world.

And coming back to 9V pedals: I didn't check your equations too close because I "know" that typical JFET spread is very-large compared to a 9V battery. Some very common parts can have Vto to 8V, which just won't work under a 9V rail. They must be run at low bias to leave room for swing, but then the current is some large fraction of Idss, which may vary 4:1 between "same" parts. Even the 3V part I used above requires very different components than your 1V 1mA part. So while the math may be exact, when you work the math for all possible variations, many of your devices will bias-up too far out to be clean, and some so far-out they won't even fuzz right.

Can you tell I've seen too many circuits work badly because the design was not robust? At your stage of education, I'm being too fussy. But if you stay on this path you may learn to appreciate robust design.

[PRR]

> I did choose a higher Id for higher gain

BTW: in field-effect devices (including tubes), resistor-loaded, fixed supply voltage, your maximum low-frequency light-load Voltage Gain is always at the -minimum- current you can get away with.

Assume load resistor absorbs some fraction of supply voltage. Near half for large output swing, maybe 80% for max gain with small swing.

Then resistor value varies inversely with current. Twice the current is half the resistance, which for constant Gm suggests half the voltage gain.

Gm is never constant as current varies. It must go to zero at zero current. How does it change in between zero and some high useful current?

In classical JFETs, Gm varies roughly as square-root of current. Twice the current is 1.4 times the Gm.

Taking half for load resistor change and 1.4 for Gm change, we see that double the current gives 0.7 times the voltage gain.

Conversely, shifting from 1mA to 0.1mA tends to give 3 times the voltage gain.

The no-free-lunch is the inevitable load. There is no point going to 0.1mA and say 50K DC load if you must drive a 10K external load. Or if you want treble to 20KHz while driving even 10 feet of cable (or 6KHz gitar and 30 foot cable). OTOH, a fat FET at 30mA is liable to give much lower voltage gain than at a more audio-reasonable 1mA.

And if you want GAIN, clearly two cascaded 1mA stages beats heck out of one 2mA stage.

[Sofl]

It will take me a little while to fully digest what you've said. It has been my intention from the very beginning to design around device variations from a practical standpoint. I don't like the idea of having to find the "magic part" to make a circuit work, it seems wasteful to build a circuit that may not work with the handful of parts you've got in your toolbox....

So I have spent some time with various resources (AN-102, ie trimless biasing) and I am seeing that I must sacrifice some gain to achieve a consistent reliable result across a spectrum of device variations, and I'm okay with that. As you've said, multiple gain stages are an option to keep on the table....



Sofl