Phase 90 Speed Indicator Led Question

[Slade]

Hi,
I was just wondering if there could be a way to make the speed led in the Phase 90 (yes, the one that you connect through a resistor to pin 7 of the LFO OPAMP) to act as the one in the tremulus lune, because this led only gets two states: On and Off, but you don't have a "gradual" indication as with the tremulus lune. I know they're different LFO's but maybe there could be something to do with it. I'd appreciate if you can give me a guide.

Regards,

Fernando.-

[GibsonGM]

If the Phase 90 doesn't put out a sine-like wave, then this will probably involve an R-C network and will use the discharge of a capacitor to make the 'swell' when the wave drops back abruptly....

[daverdave]

I think you're getting the schmitt output there, I'm not that well up on this circuit as I generally prefer seperate opamps for the schmitt and integrator. You could try putting it in parallel with the 15uF cap, not sure how it'll affect the circuit though, but it should give you the discharge of that cap.

[daverdave]

Sorry, you should stick in a current limiting resistor in series with the led as well.

[R.G.]

The P90 LFO uses a single capacitor as a good-enough integrator. Works well enough for the application and is cheap. That's where the "triangle" wave appears. You can't load that down or it messes with both speed and sweep range. The trick is to buffer it and use the buffer output to drive the LED.

The buffer also needs to work on the DC offset, because the average DC level of the triangle is the same as the bias voltage on the sources of the FETs. You might, maybe be able to get good enough operation by tying a JFET gate to the integrator capacitor, the drain to +9, and the source to an LED or LED+resistor. The "might" includes considerations like the LED's voltage (can't use a 3-4V blue or white LED there, not enough voltage) and the Vgsoff and Idss of the JFET. J201 is not a good one for this job, the Vgsoff is too low. The same JFETs you used for the phasing might work fine, as these tend to have Vgsoff of about 3V. If you're using a mod which has the bias voltage higher than the stock 3V, it gets easier. But JFETs vary a lot, so this approach is going to rely on picking the right JFET and right LED, maybe also the right resistor.

The buffer needs to have an input impedance that's big (which translates as "at least ten times bigger") compared to the biggest value of the speed pot. That means that you're kind of limited to JFETs, opamps, and darlingtons. An opamp could be set up to do this very well, with just the right offset and gain to make the LED fade in and out, but there's some tinkering with values needed there too, because it depends on the gain needed, current needs of the LED and LED voltage too.

Good place for some tinkering on a cold winter night!  

[daverdave]

That's very insightful, I thoght that just sticking in an led wouldn't be a good idea. So what you're suggesting is kinda like having an extra jfet, in parallel with the rest of the jfets in the stages, that's driving an led, set up as a current amplifier?

[R.G.]

Kinda. What I'd try first is using one of the matching rejects JFETs. I'd connect the gate to the integrator cap, the drain to +9, and the source to a resistor to the LED, to ground.

The gate will follow the capacitor/LFO signal up and down as long as you don't clamp the source to some impedance to ground that the source can't pull up. If it's clamped, the gate will rise to above the source by a diode drop, the gate-source is no longer reverse biased, and the LFO will be cut off. But if the source can pull it up...

Oh, duh! How silly is that? Belay that. Just redesigned in my mind while typing.  Hang on, this will be chaotic as I type stream of thought.

Put a resistor from source to ground, and the LED from +9 to the drain. Now the gate follows the LFO. The source is driving a resistor to ground, so the resistor current is the source voltage divided by the resistance. The same current has to flow through the drain - and therefore the LED.

Now the gate wanders from about +2 to +4 (around a 3V zener voltage) and the source stays about 2-3V more positive than that. Call it 4V to 6V. The drain needs to be at least one LED voltage below +9 to light the LED, but as long as that's true, then the LED voltage doesn't enter into it any more. The current that flows in the source also flows in the LED.

But the current in the source is Vsource/Rsource. Vsource is 4 to 6V, maybe, depending on JFETs. That's not a huge difference, and the LED in the drain won't turn off. OK, put a resistor and a "dummy" LED in the source. The dummy LED eats up a couple of volts before letting any current through and the resistor now sets the current. The drain-side LED now turns almost completely off and the resistor sets the max current, as does the LED Idss.

In this setup, a low-Vgs device *is* a good idea, and the J201 will work OK, as long as it's Idss is big enough; J201 is a low-current JFET.

Hmmm... OK, third iteration. The source side LED has the same current in it as the drain side LED. So the source side LED can be back at being the main LED, ditch the drain LED, and use a resistor between source and LED.

The sticky part here is getting the right mix of JFET Vgoff and Idss to get the LED to turn on enough when the gate goes up and off when the gate goes down, with the LFO being offset from ground.

Of course, the tinkering I'm thinking of depends heavily on the value of the bias voltage setting the average DC level of the LFO waveform. If you use one of the higher bias voltage tricks, like a 5V zener for bias, then the juggling has to be redone for the new bias voltage.

[Slade]

Thanks you, guys, specially R.G., thanks for taking the time to think of it, although I can't still understand everything you're saying, specially that things about Idss and stuff... Hopefully I'll be working on it soon. My intention is to share a new layout that includes the most popular mods: Extra Stages, Ramp LFO and a working Speed/Sweep Led, there's a lot of people and new Diyers interested in this.

Regards,

Fernando.-