Using a Latching Relay w/ 4013

[electrosonic]

After looking at other people's schematics I have come up with this as a first attempt.



R1 and R2 would be 10k, C1 and C2 sized for a appropriate pulse width.

D1 and D2 protect the transistors when Q or ~Q go low so current doesn't get pulled through the base of the transistor.

1) Is this  a reasonable approach?

2) How long is pulse required to switch the relay? The datasheet states the "set time" as 3ms max, or is that the length of the switch bounce of the relay.

Relay is Panasonic TQ2-L2-9V datasheet is here...
http://files.me.com/electrosonic/b5k37t

Thanks,
Andrew

[PRR]

Are you sure 10K is low enough? (You don't say CMOS voltage, relay voltage, or relay current.)

What is the R-C product needed to get 3mS?

With 5V on CMOS and 0.7V at Base, you may not need nominal 3mS R-C product, but figure it and see if you can afford the cap or need a finer computation.

[electrosonic]

More details...
9 volt supply, CMOS 4013. 

I guessed that with a 10k resistor the transistor would saturate when the cap starts to charge (when Q goes high)  creating the start of the pulse. I am not sure how to choose c1 and c2 to set the duration of the saturation ie the length of the pulse. I do have a scope so I was planning on making a test set up to measure it directly.

I also haven't considered slowing down the rise time of the pulse to minimize switching noise in the relay as I have seen others do.

[R.G.]

More details...
9 volt supply, CMOS 4013. 

I guessed that with a 10k resistor the transistor would saturate when the cap starts to charge (when Q goes high)  creating the start of the pulse. I am not sure how to choose c1 and c2 to set the duration of the saturation ie the length of the pulse. I do have a scope so I was planning on making a test set up to measure it directly.

I also haven't considered slowing down the rise time of the pulse to minimize switching noise in the relay as I have seen others do.

When all else fails, get out a datasheet.

The CD4013 datasheet says that the minimum current out at 5V, logic high, is 0.51ma at 25C at an output voltage of 4.6V; and at 10V, it's 1.3ma, producing an output voltage of 9.6V. So if you're using 9V, which from a battery may go as low as 7V for a non-fresh battery, then you have (guessing between 5V and 10V supplies) 0.8ma out at 6.5V.

The datasheet for the relay says it needs 6.75V across the coils and 6.75/405 = 17ma to flip on either coil, and that it has to be that for about 2mS to ensure it flips.

Low batteries get down to about 7V, and the transistor has to saturate to under 0.25V to get it there. The 2N3904 will saturate to 0.2V at a gain of ten, so it will barely do it. It will only do this at a current gain of ten. So the base current to get you there is about 1.7ma.

Back at the output of the CD4013, you need to produce 1.7ma to ensure saturation. This is larger than the CD4013 can be guaranteed (by guessing! I mean, interpolation.) to deliver at lower battery voltages. But we'll forge ahead assuming that you'll let it give up with a battery fresher than 7V. The 4013 can't be guaranteed to produce 1.7ma under any circumstances. That means you have to let the saturation gain of the 3904 rise, and that means the Vcesat rises. Which again raises the minimum Vsupply that can operate your relay.

What I'm getting at is that the 4013 is an awfully weak drive for bipolar transistors in this setup. The necessary pulse time makes it worse.

A better choice would be to change the NPNs out for TO-92 MOSFETs. This eliminates the base current issues entirely, and makes the time constant of the pulse into the gate independent of the operation.

Another better choice would be to make up a toggle flop out of CD4049s, which have a much bigger current output. Each section of the 4049 can output about 3.6ma and could drive the transistors' bases.

It is very difficult to ensure the time of the pulses from a resistor and cap when it drives a base as you have shown it. The "pulse" is really a spike to the supply which immediately decreases exponentially. The decrease lowers the effective saturation gain of the NPNs as time goes on, so the transistor - if it saturated to start with - pulls slowly out of saturation as the pulse decreases. The actual time the collector spends over 17ma and under 0.25V is hard to predict, given the spread of transistor gains.

Your intuitions are good, but you need to dig out some datasheets, and look at the guaranteed minima and maxima under the circuit conditions. Otherwise, the circuit will work sometimes, but not others.

[electrosonic]

Thanks for going through the design process. That all makes sense, switching to driving the relays with a BS170 mosfet will simplify things.

I have messed with using a CD4049 as a toggle (like the geo relay driver), but  I could never figure out a clean pcb layout of the circuit.

Andrew.

[R.G.]

Thanks for going through the design process. That all makes sense, switching to driving the relays with a BS170 mosfet will simplify things.

You're welcome. The reason I'm so familiar with this is that I... um... have made the mistakes before...  so I know where some of the pitfalls are.

I have messed with using a CD4049 as a toggle (like the geo relay driver), but when I could never figure out a clean pcb layout of the circuit.

Here's a hint. The three inverters on each side of a CD4049 are arranged all pointing in the same direction. So you connect (for instance) pin 3 to pin 4, and 5 to 6. Put the feedback resistor from 4 to 7. Connect the "next state" R-C to ground from pins 5/6 to ground, and connect the momentary switch from cap-to-ground to pin 7. Output 1 is on pin 4, output 2 is on pin 2. The other side can be used for another flipflop or current buffering/oneshots/ other MML (Mickey Mouse Logic) as needed. This stuff is all dredged out of Gary Lancaster's CMOS Cookbook, one of the small number of bibles that exist.

The CD4049 is one of my favorite ICs. Sometimes I'll use the schmitt-trigger hex inverter chips like the CD40106 or CD4584 for the same thing if I need guaranteed snap-action to clean up a slow input pulse, but the 4049 is the workhorse.

[PRR]

> I do have a scope

OK, but not essential.

You need to clack the relay. Set up a test rig with assorted caps. Listen for the click or monitor with an ohm meter. Find the cap which barely clacks the relay. That's your bare minimum.

What is the maximum pulse? You can probably leave the coil energized "forever". Well, you may have to let the pulse decay before the next opposite pulse. There may be a maximum pulse for over-heating. And if power is limited you want to keep pulse-time small. (If power is not tightly budgeted, don't use pulse relays.)

So if 1uFd clacks, on the bench, with fresh or weak battery, use 2u or 5u cap just to be sure. The approximate 15mS pulse won't restrict your switching speed, burn the coil, or run-down your battery.

> When all else fails, get out a datasheet.

That's cheating.

> The datasheet for the relay says it needs 6.75V

Andrew said "9 volt supply", but not which relay.

There's a 4.5V model, so you could have gobs of voltage. But your analysis says the current is also marginal. That's where I was going with "sure 10K is low enough?" But it's been a while since I made these mistakes, and with original-recipe CMOS you can't go a lot lower and have for-sure drive.

The 4049 buffer is an old workhorse.

Some newer CMOS families have a lot more current.

The logic-level MOSFET is a great tool here.

So is another CMOS gate, because the threshold voltage is a (roughly-) known fraction of the supply voltage and the input impedance is infinite. R-C between CMOS buffers is a classic pulser.

555 will take an edge, output a nice square pulse with ample current and known duration. What's the dual, 556?

There used to be a part made for driving relays from TTL/CMOS, six 30V 0.5A Darlingtons with bleeds and clamps. Huh, memory is not too bad and the darn thing is still offered: http://focus.ti.com/lit/ds/symlink/uln2003a.pdf

> very difficult to ensure the time of the pulses from a resistor and cap when it drives a base

The base impedance is low and very variable. For the current we need it is much less than the 10K, that's only for pulse recovery (because the base reverse impedance is infinite and the cap would "never" recover).

There's a trick. Collector current is about Beta times base current. Therefore if base is driven full-rail with 1uFd, the collector acts like 100+uFd rammed to the rail. If you charge 100uFd to 9V and dump it in the coil, will it switch? Some such scheme will certainly work. Obviously it is still a brutal non-optimal pulse, with uncertainly due to Beta variation.

> dredged out of Gary Lancaster's CMOS Cookbook, one of the small number of bibles that exist.

"Don".

Yes, absolutely worth every penny. $4-$14 for reader copies at ABE.
http://www.abebooks.com/servlet/SearchResults?sts=t&tn=CMOS+Cookbook&x=0&y=0
For simple work, I would favor a beat-up 1977 copy rather than the recent re-issues.

[R.G.]

What is the maximum pulse?

2mS from the relay datasheet.

(If power is not tightly budgeted, don't use pulse relays.)

Amen.

> When all else fails, get out a datasheet.
That's cheating.

Andrew said "9 volt supply", but not which relay.

Actually, he said:

Relay is Panasonic TQ2-L2-9V datasheet is here...
http://files.me.com/electrosonic/b5k37t

with original-recipe CMOS you can't go a lot lower and have for-sure drive.

Yep. That's why the bells went off in my head. I've had bad experiences with relays and CMOS driving NPNs.

There used to be a part made for driving relays from TTL/CMOS, six 30V 0.5A Darlingtons with bleeds and clamps. Huh, memory is not too bad and the darn thing is still offered: http://focus.ti.com/lit/ds/symlink/uln2003a.pdf

Still is, and there are extensions to the family.

I have a rule of thumb that when I'm trying to figure out whether to use transistors or ICs, I count pins. For two relay drivers, it's close. Hard to call that one. Over three and the IC is the way to go, especially since it has its own internal input limiting resistors. I know you know this stuff Paul, I'm just trotting it out for the benefit of the audience.

> dredged out of Gary Lancaster's CMOS Cookbook, one of the small number of bibles that exist.
"Don".

Yeah. Him. 

[PRR]

> count pins.

Worth repeating. On nickel and dollar parts, COUNT PINS. Including resistors and such. In DIY, the value of your labor exceeds the cost of parts, and labor (building AND debugging) is related to pin-count.

> the IC .. has its own internal input limiting resistors.

As you may recall, the 1970s ULN200x parts did NOT current-limit. I know, because one of my swifter debugging incidents was finding a crater and shiny silicon where it should have said "2003". Drive a short and the hot silicon blows the epoxy right off. They may have added current-limit, and I see they suggest newer parts with all the bells/whistles.

What is the maximum pulse?

2mS from the relay datasheet.

No, the MAXimum pulse. Can we leave the coil energized for much longer than nominal 3mS? Thereby reducing tinker-time/energy?

The datasheet gives no maximum time that I can find. It shows coil temperatures which only make sense if the coil is energized for a "long" time; they may be "ultimate" temps. And they are not very high. In a boiler-control or an oil-well probe, I'd do some numbers, but I think "forever heat" is a non-issue any place you'd want to play.

Then MAXimum pulse length is limited by operational issues. If you change setting once per song the pulse must be less than 3 minutes. Or because you will probably occasionally bobble finding the right setting, "much less than a second" so by the time you know it's wrong it is ready for another jolt.

Then the minimum is 3mS, the maximum should be well under 300mS, there's a ton of leeway in pulse width. Point is: no great precision needed, no 'scope needed. Of course I would watch the green wave, but I'd mostly go for "enough to clack, plus 3X just to be sure".

The other limit on pulse-width is implied by just using a latching relay. Total battery drain. If you changed once a second with a 0.5S pulse, you may as well use a non-latch relay. Once a minute with a 100mS pulse, 200mW nominal power, 0.3mW average power, or 0.04mA average. This is probably "small" compared to all other power drain in the box, typically 0.4mA-40mA. Yes, you could sharp-pencil for 10mS pulse, get average drain down to 0.004mA.... but how often are we this power-starved? Depends on the power-source (solar-cells?), what else is in the box (starved FET? Vacuum tube?), how often it will switch (relay-vibrato versus a power-off thump-blocker).