Jfet bias

[PRR]

Pete, you are in a bad crowd.

Common JFETs are hard to use under 9V supplies. That's why we always see trims, and why there is always a "Help!" thread on the board.

Think outside the (stomp)box. Learn how to do it Right. -Then- learn what compromises and fiddles must be done to work at 9V.

Basic Fact: it takes 1V-5V to turn-on a JFET. This bias is an input signal. You are talking voltage amplifiers. You want the input smaller than the output. For easy biasing you want the input variation to be much smaller than the output. The output is constrained by supply voltage. The output should be much greater than the 1V-4V range. If you know your JFET's on-voltage is low, 1V or so, you can try 10V or maybe 9V. If you just buy any handy JFET, you may need 40V or more for an "easy"-bias happy amplifier. But you should respect the 30V-40V breakdown of most JFETs. A 24V supply is a better experimental platform than a 9V battery.

This business of varying the Source load resistor is bogus, a not-100%-successful compromise with available JFETs and 9V supplies. The Basic Concept for an audio voltage amplifier is: a 3-way tug-of-war between the device (JFET), the DC load (Drain resistor), and the audio load (tone-stack, pot, next stage, etc).

In this tug-of-war, the amplifier should dominate the load. We select the Source resistor 1/2 to 1/5th the load. Say the load is a tone-stack. Using Fender Twin values, this may be roughly 220K. Therefore the Source resistor should be 110K to 44K. 47K is a standard value, use that.

In the tug-of-war between Source resistor and JFET, both contribute to output, we want a "fair fight". We set the Drain voltage about half-way up the supply voltage. For 24V supply, near 12V. You can go higher or lower, 1/3rd or 2/3rd, no big difference until overload happens, so start at 12V. This means 12V across 47K or about 0.25 milliAmps current.

At peak negative output the JFET should be able to pull nearly the full supply voltage across the 47K. 24V/47K is 0.5mA. we must be sure the JFET can pass 0.5mA. We select an Idss greater than 0.5mA. This is not usually a problem for common JFETs with these values.

If Idss is over 0.5mA, and we zero-bias the JFET, it will suck the 47K down to zero and get jammed up. We need to apply a bias voltage to get it to 0.25mA. We do this with a Source resistor. Most JFETs will bias-up with 1V to 5V. The current should be 0.25mA. So the Source resistor should be 1V/0.25mA= 4K to 4V/0.25mA= 16K. For an unknown JFET, tack about 8K in there. If 10K is handy, use that.

I just simulated such a stage, 24V 47K 10K, with the first simulated JFET I found in my sim library. It biased-up at 0.256mA. I tossed in another, it biased to 0.131mA. With no source bypass cap, the gains were 4.3 and 4.8, because the large source resistor is heavy NFB. With source bypass cap, the gains were 53 and 100, varying with the specific JFET used but not a gross difference.

The second JFET I tried, which gave 0.131mA, biased the Drain up at 18V, 3/4 of the supply voltage. The un-fair tug-of-war gives early clipping and marginally lower gain than we might find. Changing the Source bias resistor to the low end of the range, actually 5K, gets 0.252mA and a gain of 130.

The assumed 220K load is "easy". Say you wanna drive a 10K pot. You need more current. Select your Drain resistor for 5K to 2K. 3.3K is a standard value. To get 12V across it we need about 4mA at idle bias, 8mA maximum. We must find a JFET with Idss greater than 8mA (which may be more than most JFETs sold for small-audio are sure to pass). Assuming the bias voltage is probably 1V-5V, the Source resistor must be 1V/4mA= 250 ohms to 5V/4mA= 1.2K. 500 (or 470 or 560) ohms would be a good trial value for the Source resistor. This sims to a gain near 30.

And that leads to a basic truth for most resistor-loaded voltage amplifiers. You must have enough current to drive your load. But you don't want much more current or the gain falls off.

A trade-off to get gain back is to increase supply voltage. Going up gets unreasonable very quickly. However going down gets pretty sad as supply voltage gets near device bias voltage. And 1V-5V bias JFETs under 9V battery is a very tough design problem, usually requiring close JFET selection or hand-trims with some untrimmable JFETs.

[phector2004]

cool!

I know I'm hijacking this thread with my questions/attempts, but are there any good ways to estimate the load? What if the load is the output?

Pete, you are in a bad crowd.

Don't tell my girlfriend's parents!!! 

[petemoore]

  Pete, you are in a bad crowd.
  Yes, but I think if I work with them some more they'll let me in  on some of the cool-o-mojo.
  I can't thank you guys enough for the explainations, definitions and Jfet experience/understanding !
  PRR has once again initiated an electronic epiphony !
  With fresh inspiration, renewed interest, and the empowerment of improved understanding/comprehension, the ROG Fetzer test-rig for Idss/Vp gets put together and joins the Jfet crusade ! That, and some variance in the power supply should allow me to have "Jfet and the Jfets" work well with others.   

[brett]

Hi Pete and all....
there are two ways to get involved with the math.
1.  enter the formulae above into a spreadsheet and use the solver to optimise one of the parameters.  To do this you will need at least one point on the Vgs - Id relationship.  I set this up some time ago, but I never use it.
or
2. use some rules of thumb.  From memory, I calculate things roughly like this: (i) choose your device: the more negative the Vgs, the lower the maximum gain (J201 with -1 V can give more gain than MPF102s with Vgs of -5 V),  (ii) chooose a drain current and resistor.  If you go for plenty of current you can assume the JFET is turned on and its resistance is low (a couple of hundred ohms).  A mA is often a good amount of current, so for Vd = 4.5 V, that's 4.7 kohms.  (For Id less than 0.1 mA these rules won't work too well as the JFET resistance will be high), (iii) now that you know the Id choose Rs so that the JFET is well "on".  e.g. for a J201 with a Vgs(on) of -1.5 V, I'd select a Vgs of -1 V (at 1 mA), and use a 1k resistor for Rsourse (a very familiar value !),  then (iv) choose a bypass cap and resistor to  get the gain you want (gain is approx Rd/Rbypass e.g. 6.8k/0.47k = 15).  There is a limit to how much gain you can get, so it's no use using an Rbypass of 0.01 k.  The cap (in uF) x the resistor (in K ohms) shouls be at least 10, so that bass doesn't roll off too much.

just my 2c...

[PRR]

> the more negative the Vgs, the lower the maximum gain (J201 with -1 V can give more gain than MPF102s with Vgs of -5 V)

True; but this follows from the concept of "input". If a smaller voltage will give a full range of bias, a smaller voltage will give a full range of Drain swing (i.e., gain).

Actually, you want V(t) +and+ Idss. If a part has a huge Idss, far more than you need, you will only use a small part of the V(t). However the interaction makes my brain explode.

> its resistance is low (a couple of hundred ohms).

Not sure what you mean by that. In any normal amplifier use, the FET is worked in the "pentode range", the dynamic "plate impedance is infinite (well, very-very high, higher than any likely load). The static plate impedance is, as you compute, around 4.5K for 4.5V 1mA; but there's no direct way to put that in the math. In fact what you do is set-up the gate-source voltage for about 1mA, and the FET will do that for any source-drain voltage from a few volts up to its ~~30V limit.

> For Id less than 0.1 mA ....

Just FYI: an UN-loaded FET's voltage gain goes up with decreasing current. For constant load-resistor DC drop, the resistor goes up directly as current goes down. However the Square-Law Gm goes down as square-root of current. So from 1mA to 0.1mA, load goes 4.5K to 45K, Gm may go from 3mS to 1mS, effective source resistance goes from 300 to 1K. The ratios 4.5K:300 and 45K:1K suggest the gains: 15 and 45.

Don't take this to absurdity. If the load is 45K, the 4.5K case is hardly loaded, the 45K case is heavily loaded. Actual gains will be more like 13 and 23. Still different, but also consider the reduced maximum output level. 4.5K driving 45K can swing 90%, 45K driving 45K can swing 50%.

[Eb7+9]

Basic Fact: it takes 1V-5V to turn-on a JFET.

Pete is indeed in a bad crowd ...

[Plexi]

I'm suffering a lot with this thing...
I'm trying to understand without any succes.
Using the Echoplex Preamp for example, 22k dr, 3k3 sr:

If I have:
- 2N5457: 2,5 to 3,5 V at drain.
- BF245: 4,5v at drain.
- J201: 6v or more at drain.

The first two works great, but with J201 I have to reduce source res to 1k5 or 2k to work.
If I use less than 3k in source with 5457, it distort in bad way.

There's something that I'm not understanding...it's necesary to get the half of the voltage provided in Drain?

[PRR]

> I'm suffering a lot with this thing...

And bumping EVERY thread with a JFET reference.

Why?

> .it's necesary to get the half of the voltage provided in Drain?

No. Only that the drain not be slammed to the floor or ceiling (zero or B+).

[Plexi]

> I'm suffering a lot with this thing...

And bumping EVERY thread with a JFET reference.

Why?

> .it's necesary to get the half of the voltage provided in Drain?

No. Only that the drain not be slammed to the floor or ceiling (zero or B+).

First of all: thank you for your time and help. 

Can I ask: is it wrong to bump a thread? Do I bother somebody that way? 
I really ask ... because I'd rather to bump a thread, before to open a new one to talk about the same thing that was talked in 20 threads.

That's why, and because I'm not bother anyone.
Don't get me wrong 

[PRR]

> is it wrong to bump a thread?

No.... but you have been bumping a LOT of threads about JFETs all week.

Which values are the most important to compare JFets?

I'm suffering a lot with this thing...

I'm dealing now of understand a simple way to bias a Jfet...

...re-biasing a J201 in a Echoplex preamp was all to discover about Jfets...

Hi everyone...
Here's another update of Plexi's diary of a Jfet (¿)

Hi everyone ...
Here's another update of Plexi's diary of Jfet (?)

Hi everyone...
Here's another update of Plexi's diary of a Jfet (¿)

[Plexi]

Is that bother you?

[bluebunny]

Why don't you start a "Plexi's JFET questions" thread?  Necro-posting largely the same question to a whole bunch of ancient threads is not a great idea: many of the previous posters have gone; you can't keep track of the answers; we can't keep track of the answers.

[Plexi]

Thanks for your patience, bluebunny :-)
You're right, thats was the idea when I opened the thread about the EP preamp (the same thread from were PRR has quoted 3 times the same message..Idk......).
I've made some coments (aka 'bump') in the "plexis diary of a Jfet" about my updates. But it seems that bother anyways.
It wasn't my intention.

[PRR]

> PRR has quoted 3 times the same message..Idk....

No, I quoted very carefully. You posted the same phrase twice in one message, once in another in the same thread.

[Plexi]

> PRR has quoted 3 times the same message..Idk....

No, I quoted very carefully. You posted the same phrase twice in one message, once in another in the same thread.

You're right, damn Tapatalk...
Corrected!
I hope you haven't bothered by my typo, too. 

Anything else, good sir?