Partial CE-2 Analysis

[panterafanatic]

I've been looking at the CE-2 schematic for a while. And D1 and D2 confuse the bejesus out of me. I can think of only a couple reasons as to why they're there. The first is to utilize the DC offset caused by the diode, but still allowing AC signals to move freely. And the second is if the diodes provide some sort of isolation, but I'm not sure how that would work if it was possible. The setup of Q4 and Q5 is something I've never seen.

Can anyone shed some light on this for me?

[PRR]

The MN3101 clock driver is intended to self-oscillate at a fixed frequency.

The Q4 Q5 contraption somehow over-rides that to give variable frequency. So you _don't_ look at D1, or D2, or Q4, or Q5.... you also have to see the internal inverters, have basic NMOS/CMOS inverter-oscillatior theory, and probably know some dirty tricks.