Help!! Mu-Doubler debug?

[markeebee]

I've been very lucky, never had to shout for help before, but this is driving me mental.

Mu-doubler from RG's schemo....
http://www.geofex.com/Article_Folders/jfetdoub/mudoubler.htm

....and MarkM's layout
http://www.aronnelson.com/gallery/main.php/v/MarkMs-Gallery/album15/album76/Mu_Doubler_LAYOUT.gif.html

Using 2N5459's.  Ordered as matched set, subsequently confirmed by JFet matching fixture.  Used a 470R bias resistor instead of 510R.  Used parallel 1M and 470K (~ 320K) instead of 330K gate resistors.  

D,S,G voltages:
Q1  7.72, 1.34, 0.00
Q2  9.13, 5.00, 2.28
Q3  2.63, 1.36, 0.00
Q4  2.63, 1.36, 2.03

"Dry" output is just that.  No noticeable difference from straight through signal.

"Doubled" output definitely isn't that.  It's very, very faint, have to turn the amp up very LOUD to hear anything at all, and there's no hint of octaving (is that a word?)

I've tried it without pots.  No difference.  Cleaned up and reflowed any remotely dodgy looking joints.  No difference.

What am I missing?

[markeebee]

[earthtonesaudio]

D,S,G voltages:
Q1  7.72, 1.34, 0.00
Q2  9.13, 5.00, 2.28
Q3  2.63, 1.36, 0.00
Q4  2.63, 1.36, 2.03

Q1 is close enough, Q2's gate looks a little funky but the source is fine so it's probably okay.  Q3 is perfect, Q4 sucks.

I think the schematic contains an error.  There should not be DC coupling between Q2's source and Q4's gate.  Put a cap in series with the 100k blend pot to restore bias to Q4.  That is the biggest problem I see.  Sort that out and if it's still dodgy we'll go deeper.

I've tried it without pots.  No difference.

Do you mean you removed the blend pot, attached a DC blocking cap, and then listened to the output at Q2's source?  If yes then my above assumption may be incorrect, but I still believe the schematic is incorrect.

[markeebee]

Thanks Alex

I'm at work at the mo so I can't try anything for the next couple of hours.  The last thing I did was connect Q2 Source and Q4 Gate to either side of a spdt, rather than the blend pot, thinking I could switch between dry and effect in isolation from each other.

So, if I'm listening to Q2 Source directly, and the blend pot is entirely disconnected, there should be no coupling between Q2S and Q4G.  Should there?  Or should I have a cap there anyway?

I've been staring at this thing too long, and nothing makes sense.  It's just like life.

[markeebee]

Aha, though, but, so.

With the blend pot disconnected, there's no way that there can be DC at Q4G.  Especially as Q1S is 0v.

So I'm guessing I've got one of those mythical mullered transistors in Q4.  Which is odd, because I'd removed all the transistors, tested them ok, and put them back in.

Ok, leaving work early today to go and check this out......

[markeebee]

Gah!  Gaaaaaaaaaaaaaaaahhhhhhhhhhhhhhhhhh!  Gah!! Gah!!!

So pulled out Q4, which subsequently tested ok.  Replaced it with new one.  Now DSG voltages of Q3 and Q$ are all the same.

But the problem remains the same.  Very low output and no octaving.

Gah!!

[markeebee]

[slacker]

Can't really help, but for what it's worth it looks like the layout matches the schematic, so I don't think it's a layout error.

[R.G.]

Sorry - couldn't get to this right now. I'll pull out the old design files and respond as soon as I can.

[merlinb]

I also think there is an error in the schem. I don't think the o.1uF cap should be connected directly between gate and source of Q2. As shown you would only get half-mu and the output stage is not SRPP as the text suggests. To agree with the text, the cap should be connected from gate of Q2 to drain of Q3/4.

[R.G.]

OK, got some demons exorcised and got some sleep.

Merlin gets the cigar, mostly. There is an inaccuracy in the schematic, but as it happens, it's not an error.  Let me explain. Back in 2002, one of the earlier flowers to bloom was reading every new posting at geofex and introducing a NEW! BEST EFFECT IN THE KNOWN WORLD! pedal made from my notes there. This stopped when a few of them oddly enough didn't work. 8-) Refer to the earlier article "Mod your Mu-Amp" http://geofex.com/Article_Folders/modmuamp/modmuamp.htm

This is one of the little pitfalls I didn't take out. I apologize for my duplicity and not correcting it after he went away. I'll go see if I can find any others I may have accidentally left there.

I am searching for the archive with the original design and sim files in it. I should have example voltages in a bit when I find it.

The big problem I can see with your voltages is that Q4's gate is not at zero. That makes balancing the differential pair impossible, and there would be no effect. The caps leading to Q3 and Q4 gate should be blocking any DC, so both gates should be at 0V.

[earthtonesaudio]

I think I have an idea about why that Q4 gate voltage is not zero:

[R.G.]

... and that's the second cigar! 

And the bigger of the two. The circuit actually works, albeit less well, with the 100n cap between source and gate of Q2. That makes it a degenerate mu-amp, and that does work, but it's terribly sensitive to loading. But the DC comes from the missing cap to the output blend control.

With those changes, the simulator gets this: or any blend back to a sine wave.


The way this thing works is that it uses the differential amplifier of Q3 and Q4 to cancel the original signal fed into the input by feeding opposite inputs an out-of-phase version of the input signal from the Q1 phase splitter. The two inputs, being out of phase produce opposite signals at the drains of Q3 and Q4, which is then cancelled by tying the two drains together. If Q3 and Q4 did not distort, there would be zero signal at the drains. However, there is a small distortion, primarily even order, that is NOT canceled, because the second, fourth, eighth, etc. distortions add at the drains instead of canceling. This is the signal that is amplified by the SRPP setup.

It is buffered by the SRPP (as opposed to mu-amp) and fed to the 100K blend pot, which lets you blend between the buffered original signal at Q1 source and the amplified/buffered distortion products at Q2 source.

Notice that the balance of Q3 and Q4 is critical. They are canceling 99% of the signal fed to them to bring up the 1% (about) of distortion to hear. So if they're not balanced, you get almost no distortion. If they are fed non-cancelling signals, you get almost nothing. Simulators always have perfectly matched transistors, so you have to check the real-world performance with real-world parts. In practice, you need to select matched JFETs or use dual JFETs, and feed them a well-balanced phase-split signal. It helps to put a trimmer on either the source resistor or drain resistor of Q1 to allow you to deliberately unbalance Q1's output to then force better balancing from not-perfect Q3/Q4.  A good choice would be to use 2.2K for one of these resistors and 2K plus a 500 ohm trimmer for the other one. That would let you tune in Q3 and Q4.

Again, I apologize for not pulling the traps back out. I'll go update that.

I have built this, and other people have built variations and it does work. More people have built the version using the CD4007 CMOS chip, which includes a set of internally-matching-by-being-monolithic MOSFET transistors.

[markeebee]

RG, Merlin, Alex - thank you very very much.  I've made a small donation to DIYSB as a token of gratitude, hope that's ok with you.

I'm so glad that I'm only as mad as I already thought I was.  I spent many ugly hours looking at this, I think it would have been many many more before I cottoned on to the 'misplaced' cap at Q2.

So, I think it's working now.  The octave output is significantly lower than the dry output, but I can live with that.

I can't explain how/why there was voltage on Q4G.  As mentioned above, I replaced Q4 and the voltage at the gate went away, so I thought it was a dodgy JFET.  But, while I was waiting for the cavalry to arrive, I put the old JFET in a little booster circuit and it works fine.  Incidentally, I'm putting the booster on Q2S to try to match up the oct output to the dry output    Think I'll swap out the JFET, just to be sure.

Once again, thanks everybody.

[R.G.]

The very low output is an issue with this circuit. Some JFETs produce more distortion than others, and the theoretically better the JFET is at being linear, the worse it acts in this circuit.

[merlinb]

I've never heard of the MOS Doubler before- what happened to the original GEO page 

[R.G.]

Trouble finding and matching MOSFETs.

[Gurner]

The way this thing works is that it uses the differential amplifier of Q3 and Q4 to cancel the original signal fed into the input by feeding opposite inputs an out-of-phase version of the input signal from the Q1 phase splitter. The two inputs, being out of phase produce opposite signals at the drains of Q3 and Q4, which is then cancelled by tying the two drains together. If Q3 and Q4 did not distort, there would be zero signal at the drains. However, there is a small distortion, primarily even order, that is NOT canceled, because the second, fourth, eighth, etc. distortions add at the drains instead of canceling. This is the signal that is amplified by the SRPP setup.

(an old thread I know, but found it from a link pointing here from a recent thread!)....

Thanks for the explanation can you please outline what exactly it is about the Q3 & Q4 config that causes even order distortion?

Also, why are you using an active load (q2) in the drain of Q3 & Q4? (ie what does that yield over a static resistive load)

Finally....does anyone one have some linkage to the mu-doubler opamp variant alluded to in the accompanying JFET variant text?

[R.G.]

Thanks for the explanation can you please outline what exactly it is about the Q3 & Q4 config that causes even order distortion?

MOSFETs and JFETs, all by themselves, produce a slight distortion. Any simple MOSFET/JFET amplifier without negative feedback does this. In fact, so do all amplifying devices. In the case of MOSFETs and JFETs, the distortion happens to be primarily second order. The inspiration for FET doublers was that this amounts to a simple device for creating an octave up if it could be isolated and tamed.

To isolate it a bit, I tried cancelling the main signal to isolate the distortion. A differential amplifier creates two signals, each out of phase with the other. By feeding the differential amplifier a nice already-differential signal, the output signals at the drains of a FET diff-amp would be nicely out of phase. They can then be added together by simply connecting the drains together.

If the diffamp were perfect and non-distorting, the total signal would cancel, and there would be zero output. But no amplifier is perfect, and there is distortion in each of the JFETs making up the diffamp. Even order distortion (which is what I was trying to isolate) does not cancel at the drains, but reinforces. So while the main signal adds to zero (in a perfect world!), the even-order distortion adds to twice as much as either device does by itself. So the 1/2 % or 1/4 % distortion each device makes on its own gets doubled, and the distortion I was trying to bring out was isolated.

However, it's still not very big. Being only 1% or so of the amplified signal, it's maybe 10% of the total size of the input signal to the stage, if that much. It needs amplified up to being as big or bigger than the original input signal.

Also, why are you using an active load (q2) in the drain of Q3 & Q4? (ie what does that yield over a static resistive load)

And that's why the active load is there. It's to get gain, and lots of it, onto the isolated distortion signal. The active load gives more gain, simply.

Finally....does anyone one have some linkage to the mu-doubler opamp variant alluded to in the accompanying JFET variant text?

Someone may. I'd have to go look at my archives, and they're huge. As a suggestion, use a dual opamp in front of the diffamp stage to feed a more-perfectly opposite signal to both gates, then use another dual opamp on the output to take the difference of the drain currents and subtract them, with a lot of gain.

The idea is still the same - isolate the even-order distortion inherent in FETs and amplify it up to be usable.

[Gurner]

Thanks RG...this is a very interesting circuit -  ie cancelling out opposite signals & being just left with thecircuit  incurred distortions (not in the fuzz sense of the word)..... if the resulting even harmonics are low & therefore need a lot of gain to get up to a useable level.....won't the SN ratio be poor? (I'm thinking hiss here?)

Presumably you get similar even harmonic distortion happening through a JFET type opapmp?