Small Phase 90 technical question about 3M9 resistor

[Mark Hammer]

Does that resistor dictate the sweep width of the LFO?

I ask because in looking through all the various P90 schematics I have, there are a variety of values for that component, and because it sums with the 1M resistor coming off the bias trimpot.

Now, I know that varying the resistance (hence current-limiting) of that 1M unit, from less-than to more-than 1M gets you different sweep ranges, so I figure that varying the series resistance coming off the LFO ought to do the same thing.

Am I correct in this assumption, and if so, what range of acceptable values could one explore? 

Do any usable values of that resistor depend on the value of the bias resistance? In other words, do the control current contributions of the two sources (bias and LFO) need to somehow be "balanced" to sweep the JFETs appropriately?  I ask because when you look at some modulation pedals that include an "Initial" or "Manual" control (e.g., the Boss BF-2), they are arranged such that the "Depth" pot is really a panpot blending the LFO and DC-offset sources so that they never sum past some maximum (i.e., you can only have lots of one if you have little of the other, and can never have lots of both).  So I was wondering if any change to the current provided by the LFO output must be counterbalanced by a complementary change to the current from the bias source.

If I have misunderstood the circuit, let me know.

[R.G.]

You understand the circuit.

The DC offset and LFO circuits in the P90 do an interactive DC offset and sweep voltage mix.

I'd have to go look at some simulations to see what the limits are, and how that works as a function of the JFET Vgs range.

Ideally, the DC offset and sweep range would be independent, either by summing them into an opamp whose output drive the JFET gates, or by feeding the DC offset directly and capacitor-blocking the DC on the LFO sweep. As I remember it, the P90 circuit doesn't separate these either way.

The smaller the "3M9", the bigger the sweep range, but the more the DC offset in the LFO forces its way with the DC conditions on the JFET gates.

[BadIdeas]

Not to bog down your discussion or anything, but I am wanting to learn more about LFOs myself, so would like to be able to follow along. I am using a reissue of the P90 with different values, and looking at a schematic for the reissue. Would the 3M9 pot you're talking about be the 2M1 leading from the JFET gates to the LFO circuit?

I am also interested in any suggested in any suggested reading on LFOs.