Driving long delay lines without multiple clock chips?

[ElectricDruid]

Hi there,
I'm currently working on/messing about with a set of four V3205 4096-stage delay lines on my breadboard.  These are Coolaudio MN3205 clones.
There are a couple of schematics in circulation which show something similar to what I've got. One is the Build-your-own-clone 1 second delay, which uses four delay lines, but has a separate clock chip for each one. The other is Scott Swartz AD3208 delay over on GGG which only uses two delay lines, but drives them both off one clock chip.

http://www.buildyourownclone.com/analogdelay.html
http://www.generalguitargadgets.com/projects/20-modulationecho/48-ad-3208

What I'm wondering is if anyone knows a way to get more power out of a single clock chip to enable it to drive more stages? Can I buffer the clock outputs with a couple of transistors in to get more drive? What causes the limitation in the number of stages anyway?

If anyone has any clues, I'd appreciate the help.

Thanks,
Tom

[R.G.]

Each clock line is IIRC the gates of two MOS transmission transistors. The gate capacitance of the 4096x2 of these is what the clocks drive. The current needed to move the voltage on a capacitor a certain amount in a certain time is
I = C*dV/dT, where I is in amperes, C in farads, V in volts and T in seconds. If the transition time of the clock is an appreciable fraction of the clock period, the transmission gates are in the middle where they act like resistors for a relatively long time per clock, and the "buckets" in the bucket brigade get very leaky from one bucket to the next.

Bottom line: the speed at which you can drive the clocks is limited by how much current you can shove into and pull out of the clock lines, this goes up with the number of gates. Twice as many gates (i.e., two chips), twice as much current is needed at any given frequency. Four, chips, four times the current.

Human ears often fill in the blanks, and many chips are actually better than the guaranteed minimums on datasheets, so you might get away with a 2:1 variation, two chips per clock driver. But at some point Mother Nature is going to say "Enough."

So,
(1) is there a way to get more power out of a clock chip for more stages?
No. The limitation is on the power dissipated inside the clock driver package. It is what it is. You might get lucky with a stronger clock chip and a less-needy delay chip, but at some point, you're going to run out of luck.
(2) can I buffer the clock with transistors for more drive?
Yes. However, you really need to make sure that what you get when you're done with this is a valid logic signal and doesn't do funny stuff like asymmetrical rise and fall times, warbling around in the middle, and so on. Design of higher-current clock drivers from discrete devices was a special skill back in the day. Frankly, using more clock driver chips is a far simpler solution. It is not as simple as hanging on a few NPNs.

[ElectricDruid]

Thanks RG, that's very helpful.

To put some numbers on it, I'm seeing clock rise/fall times of around 200ns with 2 delay lines (8192 stages) and 460ns with 4 delay lines. The extra loading clearly does slow the edges down.

The V3205 datasheet gives a 500ns max clock rise/fall time, and a clock input capacitance of 2800pF (2.8nF). So I'm trying to drive the voltage across 11.2nF from 0V to 5V and back again inside a few hundred ns.

I guess the worst case is with a clock frequency of 100KHz, since up there the rise/fall time will be largest proportionally. Still, 100KHz is 10uS period, which is 10,000nS, so a few hundred lost at the edges isn't *that* bad!

I'll let you know if I find anything further.
T.

[ElectricDruid]

I just did the sums with the equation you gave. Interesting reading.
dV is 5 Volts, since I'm trying to get from 0V to 5V, so there's 5V of change. dT is 100nS, since that's how long I'd ideally like it to take.
C is the clock input capacitance of 2800pF times four, for the four delay lines, which gives us 11.2nF.

So we get:

I = 11.2nF * 5 / 100nS = 0.56

Presumably that result is in amps, so that's 560mA I need to provide or drain to get the speed I want. If I can live with 200nS rise/fall times, I could half it to 280mA, but it's still quite a lot of juice.
I don't know whether that makes me think it can't be done, or that it can...

T.

[MoltenVoltage]

From what I can tell you are trying to overclock the 3205 by 100x, but maybe I'm way off.

If I am, consider using multiple pins on a uC to drive separate stages, they can easily match the 5mA current output of the 3102.

[ElectricDruid]

Thanks. I might try multiple uP pins as you suggest.

You might be right about the overclocking, at least in terms of current, not speed. There's something funny going on here - something I don't understand. If the 3102 clock driver only outputs 5mA, and you put that into RG's equation, you get:

5mA =  2800pF * 5 / dT

dT = 14nF / 0.005 = 2.8uS

So according to this, the clock driver chip can't drive the delay line within spec - not even close. Since it definitely can, something funny is going on.

T.

[MoltenVoltage]

The 3205 datasheet identifies a max clock frequency of 100 kHz (@ 204.8 mS delay time)

The 3102 identifies a top speed of 700kHz

In any event, by your math, the max frequency of the 3102 is 357 kHz [2.8 uS], which is well above the needs of the 3205.

[StephenGiles]

Mmmmm I gave up maths 46 years ago One buffered 4047 drives 4 x MN 3005 in my Yamaha E1010.

Funny how "maths" as we say it in the UK has lost it's S accross the pond!!

[ElectricDruid]

Just to be clear;

I wasn't trying to calculate the RC time constant of the clock chip. The clock frequency is fine. I've got a nice sensible range from 10KHz to 100KHz. That's fine. What isn't fine is what happens to the clock edges when I start attaching multiple delaylines.

RG suggested a formula for the current required to move the voltage across a capacitor, to find the current the clock chip needs to source. Given a 5mA output from the clock chip, and a delay line clock input capacitance of 2800pf (from the 3205 datasheet) we get:

5mA =  2800pF * 5 / dT
dT = 14nF / 0.005 = 2.8uS

This means that it takes a 5mA current 2.8uS to raise the delay line clock input from 0V to 5V. Given that this is *far* too long (think 50-100nS instead) then there is something wrong somewhere. But I don't know where. RG's equation suggests you need 100-200mA out of the clock chip to get down to the sort of rise times that are reasonable. So is the equation wrong? If not, what's going on? I don't get it.

[PRR]

> 100KHz is 10uS period, which is 10,000nS, so a few hundred lost at the edges isn't *that* bad!

It depends how bad leakage matters.

I've forgot much about BBD lines.

I do recall trying to multiplex audio. Take 8 signals to an 8-way rotary switch. Turn it very fast. Put that signal over a line. At the far end, another spinning switch, synchronized, to distribute to 8 outputs.

100nS transitions on a 10,000nS period would give 1:100 or -40dB leakage between channels. That was not really enough.

Being fuzzy on BBDs, I'm thinking that 1:100 leakage each stage, times 100 stages, is 100% leakage; maybe not, but you are talking thousand(s) stages.

> The V3205 datasheet gives a 500ns max clock rise/fall time

That may be a good guide. However sometimes datasheets DON'T tell everything.

Ass-uming 2800pF and 500nS, my abacus says more like 5mA than 500mA. But maybe more coffee will find more current.

There's also "Clock cross point". They want the two phases to cross at 0.3 of some voltage. This probably ensures a "dead band" where _neither_ switch is on. That's the kind of thing that R.G. means by "a special skill back in the day". I know I have seen system clock datasheets more extensive than the chips they clocked.

Did you see this? "V3205SD ..... Only available together with V3102." If that's the deal, you MUST buy a clocker with every delay chip, and may as well use it.

[puretube]

Oh, what fun it is to do a search for:
"clock", "giles", "hammer", & "puretube"...   

[puretube]

Did you see this? "V3205SD ..... Only available together with V3102." If that's the deal, you MUST buy a clocker with every delay chip, and may as well use it.

Pure marketing...   



Tom: If you need 2 or 3 4041`s for a private project, mail me, they`ll arrive on monday... (DIP or SMD?)

[Cliff Schecht]

He could also look into some sort of multiple clocking solution. I'm sure somebody makes an IC that can take in one clock, square it up (PLL preferably), divide/multiply (if necessary) and distribute the clocks as needed. I know of some very high frequency solutions that TI offers (the CDC chips) but these all require register settings (i.e. need programming).

[Cliff Schecht]

http://focus.ti.com/lit/ds/symlink/cdcv304.pdf

[StephenGiles]

What about a CD4098??

[oldschoolanalog]

From the KISS school of "if it ain't broke; why fix it?"...
The buffered 4047 setup Stephen mentioned has been around and used for quite some time. To my (very limited) knowledge, nobody has complained about that arrangement. We're talking BBD's here. Want "Hi-Fi"? Go digital.
If it sounds OK...

[StephenGiles]

You could perhaps make a nice little thru zero flanger using a CD4098 - with one half wired as a fixed frequency clock and the other as a variable and put it in one of your little 1590 boxes - there you are, one for the weekend.

I'm not saying you can, just perhaps!!

[Lurco]

http://focus.ti.com/lit/ds/symlink/cdcv304.pdf

recommended maximum voltage: 3.6V . Absolute max. 4.3V !

[analogguru]

Take a TC427 (or TC428 with single-phase-clock) from Telcom or Microchip and you´ve got it.
This chip can drive up to 1,5A with a supply-range from 4,5 - 18 V.

http://www.datasheetcatalog.org/datasheet/TelComSemiconductor/mXvqtxu.pdf

analogguru

[JKowalski]

Take a TC427 (or TC428 with single-phase-clock) from Telcom or Microchip and you´ve got it.
This chip can drive up to 1,5A with a supply-range from 4,5 - 18 V.

http://www.datasheetcatalog.org/datasheet/TelComSemiconductor/mXvqtxu.pdf

analogguru

Dang, I was just about to suggest a MOSFET driver.

They are meant to drive the large gate capacitance of big power MOSFETS at very high speeds, and sometimes can reach peak currents of 10 or more amps. The ones around 1 amp peak will work well for this and are much cheaper.

+1