FET Biasing OpAmp

[Scruffie]

Say I have a J-FET Set up as a simple gain stage with the Voltage going to the Drain and the Output coming from it... Other than a trimmer to set the Bias, what would be the possible implications of using that Voltage to Bias an OpAmp instead of a V.Ref? I know i'm missing something because this set up doesn't seem like it could be good for the OpAmps Input, Too many voltage spikes due to the Swing?

[Johan]

no problem, just make sure the opamp of choise doesnt eat to much current to bias up,  or it might be a tuff balancing act...I'd go with a TL072  ( a 5532 might want too much if you run on 9 volt and your drain resistor is >10k)
J

[caress]

sounnnnnds interesting!

[Steben]

Opamp even doesn't need to be biased at V/2. I remember (XXL distortion?) "warp" controls that intentionally misbias the input to get mushy fuzzy sound.

[cpm]

Say I have a J-FET Set up as a simple gain stage with the Voltage going to the Drain and the Output coming from it... Other than a trimmer to set the Bias, what would be the possible implications of using that Voltage to Bias an OpAmp instead of a V.Ref? I know i'm missing something because this set up doesn't seem like it could be good for the OpAmps Input, Too many voltage spikes due to the Swing?

i cant see exactly what you want. a drafted schematic would help...

[earthtonesaudio]

Some things come to mind:

-The JFET may swing rail-rail.  Not all op-amps like rail-rail inputs.
-Probably will be easiest to make the DC gain of the op-amp unity.

Here are 3 ways I would consider:


My preference would be the mu-amp style configuration, since it doesn't need a trimmer.

[cpm]

ok, now i understand what scruffie asks

My preference would be the mu-amp style configuration, since it doesn't need a trimmer.

Could you explain a bit of that configuration?

For biasing an inverting configuration, it could be done with a R from (-) to (+) and C from (+) to ground, this sets the DC level but filters out AC (eg 100k+10uF)

[Steben]

Some things come to mind:

-The JFET may swing rail-rail.  Not all op-amps like rail-rail inputs.
-Probably will be easiest to make the DC gain of the op-amp unity.

Here are 3 ways I would consider:


My preference would be the mu-amp style configuration, since it doesn't need a trimmer.

It's not really mu-amp. In a mu-amp there is a voltage divider (to ground!) that fixes a current source (the second fet). No trimmer, but more components.
In your last schem there is no voltage dividing.
And speaking of which ... why would you use this thing? As a more simple way of connecting to an opamp, yes, sure. Buffering, yes. But the mu-amp thing ... why not with a second fet?

[Scruffie]

I just wanted to know if I was going to cause any damage doing it over a long period.

Earthtones has the idea, I have the set up working, it's basically just to avoid having two extra resistors and a cap for the V.Ref when there's already some perfectly good voltage going to waste, that happens to like being biased around 4.5V

[earthtonesaudio]

It's not really mu-amp. In a mu-amp there is a voltage divider (to ground!) that fixes a current source (the second fet). No trimmer, but more components.
In your last schem there is no voltage dividing.
And speaking of which ... why would you use this thing? As a more simple way of connecting to an opamp, yes, sure. Buffering, yes. But the mu-amp thing ... why not with a second fet?

It's true, the schem I posted is more like a SRPP stage because of the resistor.  I called it "mu amp" style because that's what people are more familiar with.

However, neither mu amp nor SRPP stages use constant current sources.  The upper FET is an active load, but the current that flows through it is modulated by the signal from the drain of the lower FET.  That coupling cap between upper FET's gate and lower FET's drain is what makes all the difference.

I haven't drawn a voltage divider bias reference, but it is there; the downward-pointing triangle represents the 1/2 supply voltage or AC ground.

To answer "why" one would use an op-amp in this way instead of a second JFET, there are multiple reasons.  For one thing, the lack of DC offset with means you don't need a coupling capacitor.  Also, the op-amp has 100% negative feedback, so it distorts less, and is capable of providing a higher maximum gain to the lower FET, while providing a lower dynamic output impedance than you can possibly get with a mu-amp or SRPP stage.  In the end this is probably going into a distortion circuit so it's all a matter of personal preference anyway, but it's nice to have a range of options to choose from.