EM3207 (v1.1) - MN3207 based EHX Electric Mistress (9V) clone

[12Bass]

However, if you look in datasheet SAD1024, you can see that this chip is designed to work with frequency up to 1 MHz. 
The manufacturer guarantees the work of MN3207 only up to the frequency of 200 kHz, and MN3007 even less – up to 100 kHz. Increase up to 1.2 Fclock -1.5 MHz to SAD1024 practically does not affect the chip.

From my own ADA clone testing, even the venerable SAD1024 loses roughly 2 dB of signal at the highest clock rate (1.3 MHz/0.2 mS) with a 4049 buffer.  Apart from the slight signal loss, the fidelity of the output at high clock rates is impressive.  It will clock even higher, but I don't see the point as there is not much musical information left up there to flange.  IMO, even 0.4 mS is short enough to produce dramatic sweeps. 

[Valentinych]

How many people, so many opinions. And each of their rights.

[Eduard_Solderingironhands]

Hello Thomas,

I don't know if R2 in my new VCO is necessary, because I haven't tried without. R1 is necessary.

Here is my MN3207:


Best wishes

Ralf

[Fender3D]

From my own ADA clone testing, even the venerable SAD1024 loses roughly 2 dB of signal at the highest clock rate (1.3 MHz/0.2 mS) with a 4049 buffer.  Apart from the slight signal loss, the fidelity of the output at high clock rates is impressive.  It will clock even higher, but I don't see the point as there is not much musical information left up there to flange.  IMO, even 0.4 mS is short enough to produce dramatic sweeps. 

It is a parallel-multiplex configuration, it has double the number of samples, so it may loose less charges or a lesser percentage of signal in charge...

[12Bass]

It is a parallel-multiplex configuration, it has double the number of samples, so it may loose less charges or a lesser percentage of signal in charge...

Not sure why parallel-multiplex would give a gain advantage at high sample rates.  AFAIK, it just doubles the number of samples per clock, but shouldn't impact amplitude versus clock rate.  Guess it might be more fair to compare it with the MN3010 if we wanted to eliminate that variable.  Reticon's somewhat different process and lower clock capacitance might have something to do with it.  Perhaps more to the point is that we're comparing a dual 512-stage BBD to single 1024-stage units which have to be clocked twice as fast to reach the same delay time.  Even if amplitude loss were the same for a given clock rate, it makes sense that the MN3x07 devices would be at a disadvantage if they are clocked at double the frequency.

[Fender3D]

The BBD's dark side is the issue the caps (buckets) tend to loose their charge, it's just a matter of time...
With double the samples you have a higher waveform "definition", so you should get a lower loss of signal since it belong to a smaller part of the waveform (assuming the same loss as normal mode).

[blueduck577]

Don't mean to detract, but I've got a question from Page 2:

Red values/line represent calculated BBD delay time (=512/(2*f_CLOCK) here)

How did you get that formula?  Looking at Reticon's datasheets, they state:

• The sampling frequency f_s is one-half the clock frequency: f_s = f_c/2
• The delay in seconds (d) is the number of samples in the delay line (N) divided by the sample frequency: d = N/f_s

So:
d = N/f_s
d = N*(1/f_s)
d = 2N/f_c

We have this information on the second page:

If you take a look at page 2 of this thread you will see that Fclock (Fcp) of the vintage EM goes from 1280 kHz to 29 kHZ which equals a delay of 0.2 ms to 8.8 ms by the

According to my calculations, a clock rate of 1280 kHz and 512 stages would result in a delay of .8 ms, not .2 ms.

[Eduard_Solderingironhands]

Hello,

@blueduck577
In my datasheet it says "Delay is 512 clock half periods...". Further on it is defined what a clock period is.
One clock half period is 1/2 * 1/fclock = 1 / (2 * fclock).
d = 512 / (2 * fclock)

d = 512 / (2 * 1260 kHz) = 0,2 ms

Best wishes

Ralf

[12Bass]

As I understand it, the number of samples in a BBD is one half of the number of stages.  Thus, a 1024-stage device produces 512 samples, while a 512-stage device produces 256 samples. 

To determine the clock rate for a given delay time, calculate the reciprocal of the delay time divided by the number of samples.

Thus, the clock rate for 0.2 mS for a 1024-stage BBD would be: 1 / (0.0002 / 512) = 2.56 MHz
 

[Keeb]

First off, let me just start off by saying that you guys really impress me. I do not understand all your calculations and simulations but this is exactly why I love this forum. Friendly, competent people helping people like me understanding circuits!

I would also like to thank Thomeeque for replying to my PM and making it public for everyone to see (the questions he answered a couple of pages back were mine).
So, I built this thing and it passes a clean signal. The only part I substituted were the 22K trim pot, I used a 25K instead which shouldn't matter anyway. Other than that I did not use any modification (no cap parallel to C17 for instance). I built it according to the PDF but without the 100n power filtering caps. I found the correct Zener diode on eBay (neither Banzaimusic or Musikding had it).

I took measurements with all pots about half way up and the trimmers were set up to about half way apart from the 100K multi turn which I turned till the sound distorted and faded away and then dialed it back until a clean signal was passing again.

NEW VOLTAGES BELOW!

I was using a wall wart producing about 8.3V.

IC1 4558

1 2.58
2 2.52
3 1.33
4 0
5 2.13
6 2.35
7 2.10
8 8.12

IC2 MN3207

1 0
2 0
3 2.10
4 7.57
5 8.12
6 8.12
7 3.12
8 3.47

IC3 LM324

1  2.01
2  0.92
3  0.92
4  8.06
5  5.10 - 2.10
6  3.58
7  6.78
8  4.12 - 2.6 (in steps of 0.06)
9  3.64
10 3.57
11 0
12 2.26
13 2.31
14 2.32

IC4 LM311

1 0
2 2.42
3 2.42
4 0
5 8.12
6 8.12
7 8.04
8 8.12

IC5 4013

1  0
2  8.12
3  8.05
4  0
5  8.13
6  0
7  0
8  0
9  0
10 0
11 0
12 0
13 8.12
14 8.12

IC6 4049 unbuffered

1  8.13
2  8.13
3  0
4  0
5  8.13
6  8.13
7  0
8  0
9  8.12
10 0
11 8.12
12 0
13 0
14 0
15 8.12
16 0

Q1 2n3904

E 1.77
B 2.34
C 8.13

Q2 2n5087

E 7.90
B 6.96
C 2.60

D1 1n4001

+ 8.13
- 7.75

D2 1n4148

+ 2.61
- 8.05

D3 Zener 10V/5W

+ 0
- 8.13

Right off the bat CD4013 doesn't seem right but I have no voltages to compare with. Could anyone please post their voltages for me to compare?
Is there anything else I should be looking for?
The 100K trim pot regulates pin 12 on LM324 right? What should that be set to?

Once again, thank you guys for making the effort and especially Thomeeque for making the excellent layout and PDF!

[Fender3D]

0V on 4049 pin 16 is wrong
it looks like your 311 is not oscillating...

[Thomeeque]

0V on 4049 pin 16 is wrong

4049 pin 16 in N.C., I'd say it's alright..

I have to spend more time with it yet, but I can see that clock (CP1/CP2) signals are frozen (CP1 = 0V, CP2 = VCC).

The 100K trim pot regulates pin 12 on LM324 right? What should that be set to?

BBD Bias (DC at pin 3 of MN3207) should be set by this trim (RT2) to cca 4.9V* for V_CC=8.3V and fine-tuned later for minimal distortion at BBD output.

More later, T.

*

[Fender3D]

holy crap...
it is a CMOS with non-standard supply pin layout...
my bad, I did just auto-reply...
anyway you have no clock on 4013 pin 3

[Thomeeque]

 Hmm, voltage at Q2/C must be exactly same as is at IC4/pin 3 (it's directly connected), can you check it again? Maybe PCB trace is broken - it would brake clock for sure..

[Keeb]

Thanks so much guys!
Any suggestions on the other trim pots?

My circuit is only oscillating on LM324 pin 5 and 8 and I understand that's a bad thing.
According to (my interpretation of) the schematic these should feed into pin 3 of the LM324 (when in flange mode) and then go to pin 2 on the LM311.
Should pin 2 on the LM311 oscillate?

When you say CP1 and CP2, are you talking about CD4013 pin 3 and 11?

EDIT; I'll go check right away!

EDIT 2; I measured again and they are both at 2.74. Could this be because I adjusted the trimpot or should I retake the voltages?

EDIT 3; I remeasured all the voltages, quite a difference on the 4558.

IC1 4558

1 5.18
2 5.12
3 2.46
4 0
5 4.51
6 4.97
7 4.74
8 8.13

IC2 MN3207

1 0
2 0
3 4.74
4 7.58
5 8.13
6 8.13
7 3.13
8 3.48

IC3 LM324

1  2.45
2  0.92
3  0.92
4  8.07
5  2.10 - 5.00
6  3.58
7  6.78
8  2.60 - 4.40
9  3.64
10 3.58
11 0
12 4.82
13 4.94
14 4.94

IC4 LM311

1 0
2 2.74
3 2.74
4 0
5 8.13
6 8.13
7 8.05
8 8.13
IC5 4013

1  0
2  8.12
3  8.05
4  0
5  8.13
6  0
7  0
8  0
9  0
10 0
11 0
12 8.12
13 0
14 8.13

IC6 4049

1  8.13
2  8.13
3  0
4  0
5  8.12
6  8.13
7  0
8  0
9  4.26
10 0
11 8.13
12 0
13 0
14 0
15 8.13
16 0

Q1 2n3904

E 8.13
B 3.15
C 2.52

Q2 2n5087

E 7.88
B 6.96
C 2.74

D1 1n4001

+ 8.13
- 7.75

D2 1n4148

+ 2.74
- 8.05

D3 Zener

+ 0
- 8.13

[Thomeeque]

Thanks so much guys!
Any suggestions on the other trim pots?

Both set at 50% is ideal for debugging.

My circuit is only oscillating on LM324 pin 5 and 8 and I understand that's a bad thing.
According to (my interpretation of) the schematic these should feed into pin 3 of the LM324 (when in flange mode) and then go to pin 2 on the LM311.
Should pin 2 on the LM311 oscillate?

In FLANGE mode yes, range should be altered by RANGE pot (in F-M mode there is constant voltage altered again by RANGE pot). Should be close to IC3/pin 1.

Because even IC3/pin 3 does not oscillate, there is probably problem with your mode switch wiring.

Anyway, with constant cca 2V at IC4/pin 2 clock should tick (clock signals would be at cca half of VCC) and it does not, so you have problem around clock too.

When you say CP1 and CP2, are you talking about CD4013 pin 3 and 11?

Nope, CP1/CP2 signals are signals for CP1/CP2 pins (2 and 6) of MN3207. They are "born" at IC5A's outputs +Q and -Q (pins 1 and 2) and should be found all the way to MN3207 (see schematic).

EDIT; I'll go check right away!

EDIT 2; I measured again and they are both at 2.74. Could this be because I adjusted the trimpot or should I retake the voltages?

Check/fix mode switch, then set F-M mode, set maximal RANGE (IC3/pin 1 should be at cca 3.4VDC), RT3 to max as well and try to measure IC5 pins 1 and 2 (as I said, healthy DC there should be VCC/2, 4.1V in your case).

T.

[Thomeeque]

EDIT 3; I remeasured all the voltages, quite a difference on the 4558.

It's alright, RT2 sets DC bias (Vref) for both halves of IC1 (4558) as well (btw. you should measure Vref at IC1/pin 3 as well, but your DMM has probably 1MΩ input impedance so the voltage there gets divided by 2, as the DMM input forms voltage divider with R3, which is 1MΩ as well).

T.

Btw. any chance to try it with different PSU? What PSU you are using exactly?

[Valentinych]

Guys, it is very difficult to correctly configure the flanger without oscilloscope and FL-oscillator.
But if your have these devices, all very simple.  

To be configurable analog part:

1)   Input devices - on the ground.
2)   POT1 (Color) - on the ground.
3)   Trimmer RT1 - up (the scheme).  
4)   Other trimmers - in the middle position.  
5)   SW1 - in position FILTER-MATRIX.
6)   POT3 (Range) - select frequency VCO ~ 100-200 kHz.  

Then output:
1)   IC1a (pin 1) – DC ~ 1/2 Vcc (Vref).
2)   IC1b output (pin 7) –  DC ~ Vref.
3)   The emitter Q1 – DC ~ (Vref-0.7) volts, with "steps" on Fvco.   

In the input device - DC 1 kHz amplitude 0.2 volts.

Then output:
1)   IC1a (pin 1) – clean AC 1 kHz, amplitude ~ 0.6 volts.
2)   IC1b output (pin 7) – pure AC 1 kHz, amplitude ~ 0.6-0.65 volts.
3)   The emitter Q1 – AC 1 kHz, amplitude ~ 0.55 -0.6 volts. Sine, with traces of "steps" on Fvco. Perhaps a small limitation on the top or bottom half wave signal.  
4)   At Pad4 – AC 1 kHz, amplitude of ~ 0.2 volts. DC amplitude depends on the frequency VCO, i.e. from POT3 (Range), and can vary from ~0.02-0.35 volts.

Next:
1)   If the emitter Q1 AC without distortion, start to increase the amplitude of the input signal before the restrictions on the top or bottom half wave signal.
2)   Rotate trimmer RT2 to one or the other way, prior to the disappearance of distortion.
3)   Repeat several times paras. 1), 2), while the symmetric constraint upper and lower half wave signal.

Now turn the knob POT1 (Color) clockwise until it stops. Slowly turn trimmer RT1 before small excitation scheme.  To configure the analog part of the scheme is finished.  

Tomorrow will configure LFO and VCO.  
To be continued.

P.S. I hope, Thomas will not object to ...  

[Keeb]

Check/fix mode switch, then set F-M mode, set maximal RANGE (IC3/pin 1 should be at cca 3.4VDC), RT3 to max as well and try to measure IC5 pins 1 and 2 (as I said, healthy DC there should be VCC/2, 4.1V in your case).

T.

I did this and I get 3.27 on IC3's pin 1. Regardless of RT3 I get  8.12 on pin1 and 0 pin 2 on IC4.
Adjusting the range pot to minimum gives me 0.92 on IC2 pin 1.

I'm using a harley benton powerplant. I guess I could try with a battery (if I can find onw in good condition...otherwise I need to get one).

EDIT; So I realized that in both flange and in filter mode I get 0 and 8.12 on IC4 pin 1 and 2. HOWEVER if I'm not careful while probing them they switch over! Say I'm getting 0 on 1 and 8.12 on 2 and then probe 2 and 3 toghether for just a microsecond and all of a sudden pin 1 reads 8.12 and pin 2 reads 0.

[Thomeeque]

 Hmm, haven't you forgot to solder jumper connecting right* node of R30 and pin 2 of IC4 (LM311) by any chance (short one close below** LM311)?

T.

Btw. hi-res photos from both sides of PCB could help here too.

* on schematic
** on layouts