theory question: endless gain stages & harmonic content

[EW57]

I've been intrigued by the triode emulation with fets, but my background/understanding is weak, if the end goal is to add harmonic "complexity",  why (theoretically) wouldn't one just put a large number of gain stages in series with the input of each stage adjusted to minimize clipping? Does this desired complexity increase with each stage (or just noise & expense)? 

In other words, whats the sonic difference between one jfet J201 stage setup for a total of 10db gain, vs a series of 10 J201 stages setup for a total  of 10db gain?

Thanks!

[R.G.]

I've used this idea in some of my most skunk-works, invitation-only devices in custom builds. You're on the edge of something very interesting.

Things that clip/distort generally do not do so at one instant voltage. That is, there is no signal that up to X millivolts is undistorted, and at X+1 millivolts is hard-clipped. There is a rounding area where the gain goes down so that if the gain is G at X millivolts, the gain at X+1 volt of signal is G minus a little bit and over the next Y millivolts of increased signal the gain decreases from G to zero (that is, flat-line clipped).

In that range from just-starting-to-decrease gain towards flat-lining is where a lot of the interesting, musical-sounding distortions happen, before the clipping starts making harsh distortions.

It happens that tubes have a biggish range of transition into clipping if you work it right. You can mimic that part of tube behavior by being careful about what signal level you feed to a clipping stage. In the end result, it's easiest to limit the signal you feed to a stage if you clip before that stage. So an interesting case of an audio clipper is to feed it from a clipper. Ideally, you'd use a soft clipper so that you didn't flat-line the stage you're feeding. And  you'd use a soft clipper to feed the input clipper. And another clipper before that. The arrangement of soft clippers has the result of keeping the amount of overdrive into any one stage down in the range that does not hard-clip it.

Don't be discouraged if your background/understanding of emulating triodes with FETs is weak. Smart Guys have been trying to do that for decades. So far, no one is there. About once or twice a year, someone new announces that all those others were wrong but now the Smart Guy of the Moment has it right.

You do wind up accumulating noise, and it takes some good design work to keep the clipping where you want it in the face of gain variations, especially with JFETs, which are highly variable. JFETs are like herding cats.

[sault]

Not much I can add to RG, but I can offer my own humble thoughts.

There are some design considerations that will limit the number of gain stages... as I've slowly made the transition from the "theory" to the "oh crap it's the real world wtf just happened", I've begun to understand some of those things. Specifically, in a guitar pedal, some of those conditions are power supply (battery voltage drop), power consumption, and noise.


We could take a look at power consumption, power supply, and what that means for a Jfet gain stage's output...


Looking at the Energizer data sheet, while it looks at first blush that you should get well over 40 hours from a 10mA draw, I would expect that your voltage will drop off pretty quickly... looking at the stats for the 620ohm load, you can see a 2v loss after 30 hours (and I'm betting in the "real world" its not quite that optimistic!).

http://data.energizer.com/PDFs/522.pdf


Why does this matter? Let's look at a situation with ideal components and a "real life" battery. The j201's max current draw is 1mA, and you'll need at least Vp to keep it in saturation, so a maximum voltage drop across Rd of 7.5v, right? So in that case, you'll want a max Rd of 7500 ohms. ( 1ma * 7500Ω = 7.5 volt drop)  But if your supply voltage drops to even 8 volts, you have potentially just left saturation, and the circuit goes to s* (I think this is the "gating" sound that you hear with a mis-biased Jfet stage). In the real world, you would want to be a leeetle more cautious than that... reference the design process for the Fetzer Valve, for instance, where the recommendation is to leave twice Vp available :

http://www.runoffgroove.com/fetzervalve.html


Anyways, the more power you're sucking, the less time your battery will last, and the faster your voltage will drop off... and unless you've designed for it, the faster your pedal will start to suck as time goes by. Some circuits sound just fine with lower voltages (ever heard of "vintage" batteries?), but some just don't.

Does that make sense? More gain stages means more gain, but also more current draw which means less battery life and more voltage drop which means less ideal tone (ie lower signal-to-noise ratio). You can design around all of this, but there are always trade-offs to designing around "real world" non-ideal components... there is a reason, I think, why most amps and pedals use no more than 4-5 gain stages.


I hope this has all made sense, please forgive any errors or misunderstandings I have made.


Saul t

[alanlan]

I've been intrigued by the triode emulation with fets, but my background/understanding is weak, if the end goal is to add harmonic "complexity",  why (theoretically) wouldn't one just put a large number of gain stages in series with the input of each stage adjusted to minimize clipping? Does this desired complexity increase with each stage (or just noise & expense)?  

In other words, whats the sonic difference between one jfet J201 stage setup for a total of 10db gain, vs a series of 10 J201 stages setup for a total  of 10db gain?

Thanks!

The amount of harmonic complexity (distortion) produced by a single typical JFET gain stage really depends on how much of the transfer characteristic the input signal to the device i.e. vgs, covers as it swings from top to bottom (see the J201 datasheet for an example of the graph of the transfer characteristic).  Of course, if the signal clips top or bottom then distortion increases dramatically.

This is affected by a number of things (not limited to): a) the amount of negative feedback (value of source resistor and possible AC bypass cap) b) the size of the input signal and c) the bias point.  It is worth simulating a single JFET stage with PSpice or similar to gain an understanding of this.

If you use a number of stages with a smaller amount of gain in each, then the distortion will accumulate although it is impossible to know how this might actually sound compared to a single stage with equivalent gain without listening.  The amount of noise added by the JFET(s) is going to be pretty trivial, most of the noise is produced by the sheer amount of overall gain acting on both the noise seen at the input and the noise produced by circuit resistances.  So, 1 JFET vs 4 JFETs for example won't be vastly different in terms of actual noise as long as the overall gain is similar.

[R.G.]

Remember - the more time the signal spends inside the range of voltages where the gain is changing, the more interesting the sound is likely to be. The places where gain is constant or zero are much duller.

[sault]

Remember - the more time the signal spends inside the range of voltages where the gain is changing, the more interesting the sound is likely to be. The places where gain is constant or zero are much duller.

So in a way, this advocates using Jfets with larger Vp's, as that implies a larger range of "interest"?



Also, concerning noise and gain stages...

A useful rule of thumb to remember is that 50 Ω at 1 Hz bandwidth correspond to 1 nV noise at room temperature.

(thank you Wikipedia)

I think that the datasheet for the J201s implies less than a few dozen nV of noise are introduced... so that means that the noise of the Jfets themselves will be swamped by the Johnson noise of the biasing resistors. For J201s, I imagine that at least 10k of total resistance is needed to bias them correctly, so therefore each stage will be adding a few tens of thousands of nV of noise. (if 1kΩ = 400nV of Johnson noise, etc)

So... am I correct in assuming that at some point adding more gain stages means adding too much noise to be tenable?


Saul t

[R.G.]

So in a way, this advocates using Jfets with larger Vp's, as that implies a larger range of "interest"?

I'd put it another way. If the JFET Vp translates into a larger range of changing gains in that particular circuit, yes, it would say that you could get a larger range of changing gains by using a JFET with a larger Vp. The circuit around the JFET may have a lot to say about how much a JFET's Vp translates into the knee region where gain is changing. Or, put another way, the circuit may hide or expose and enhance whatever nonlinearities are there in the parts.

I think that the datasheet for the J201s implies less than a few dozen nV of noise are introduced...

For the device itself, yes.

so that means that the noise of the Jfets themselves will be swamped by the Johnson noise of the biasing resistors.

Depending on the values, materials, and circuit use of the resistances, possibly.

For J201s, I imagine that at least 10k of total resistance is needed to bias them correctly, so therefore each stage will be adding a few tens of thousands of nV of noise. (if 1kΩ = 400nV of Johnson noise, etc)

It's easy to calculate what that would be. However, using a JFET with a 10K impedance biasing network is sidestepping the screaming value of JFETs - their high input impedance. Why put up with the variability and low gain of a JFET if you don't at least get very high input impedance? This is why JFETs are usually biased with 1M and greater resistors.

After the first stage, of course, you're free to use lower source impedances into the next stage; however, the output impedance of a lot of JFET gain stages is high as well. The mu-amp "minibooster" has a quite high output impedance, and needs a buffer or a change to an SRPP stage to drive a low biasing impedance for a second stage. So you pay for that with either a added 1K resistor (to get to SRPP from mu-amp) or another bias resistor/active device to buffer the gain stage. If you're willing to settle for lower gain, you can make the drain resistor be low-ish, maybe 10K, and then you only need a 100K bias resistor for the next JFET stage to keep from eating all the gain you've already made. The noise of this stage is probably inconsequential, since the noise from the first stage is also multiplied by the second and all succeeding stages. So to a great extent, the final noise is determined by the first stage.

So... am I correct in assuming that at some point adding more gain stages means adding too much noise to be tenable?

You are, but it's much more dependent on the total gain from the input to the output than it is the noise of stages after the first one or two.

[Mark Hammer]

Remember - the more time the signal spends inside the range of voltages where the gain is changing, the more interesting the sound is likely to be. The places where gain is constant or zero are much duller.

Excellent insight.
Now I'm wondering what several Tube Screamer-like stages, with a resistance in series with the clipping diodes, might sound like.

[R.G.]

The problem with a TS stage used that way is that a TS has no limit on its output due to the 1+ term. If you drove it from a resistor into the inverting input, then yes, it will limit to the diode-drops in the feedback loop, irrespective of the gain setting.

So if you had an incoming signal of 100mV peak, you'd need a gain of 6-7 to get that signal to just breaking the diodes over. If you then attenuated the output by a factor of 6, you'd get back to nearly 100mV peak, but with any of the rounding on the top edge from the first diodes.  Now run that into a similar stage. The rounding accumulates.

However, it's all confined to the top bit of the waveform, so eventually you accrete to a flat top again.

A silicon diode's best case conduction knee is roughly from 0.45V to 0.7V, about 250mV. It would be much neater to figure out a circuit where the signal could be mapped from 0-100mV into that 250 mV where the conduction is always changing, not just changing for the top few bits of it.

[ORK]

A window-clipper or window-limiter. Whatever that might be? Soft-slicer?

[sault]

My initial thought was to expand the TS' diode network out a bit. In other words, put parallel resistor + diode combinations in the feedback network... so smoother clipping, basically.

Ie 100 mV in, gain of 20 => 2v, but with a voltage divider network of, say, a 10k and a 15k resistor, each leading to its own diode, that cuts the signal in a 40/60 split, or 0.8 volts and 1.2 volts. One is barely over the diode drop, the other isn't a terribly large amount over. Fiddling with the gain and resistor network would help... and adding more resistor/diode pairs would further shape the curve.


Does that make sense, or should I Spice it and take a screenshot?


Saul t

[R.G.]

Does that make sense, or should I Spice it and take a screenshot?

No need. There isn't much with diodes, shaping networks and opamps that I haven't tried.

[alanlan]

Does that make sense, or should I Spice it and take a screenshot?

Yes you should Spice it on the grounds that it will maybe teach you something you didn't already know and it doesn't cost anything in parts.

[petemoore]

  Instead of a long boring chant, I'll just add the caveat: Use sparingly or generously, or not at all...
  1rst stage that prepares weak guitar signal output for 'processing'.
  LM317/filtered output for each stage PS, 9vdc is 'good'...as a median voltage, perhaps one stage in a series might find 9vdc to be 'sweet.
  LV Buffer stage.
  Variable attenuators between stages.
  Varying "how much is input?'', and ''what is the supply voltage'' for each stage could lead to a very smooth 'ladder-step-distortion' in which all the steps are evenly spaced, and the accomodations for your signal [not mine] have been tailored so as to put and keep these Jfets in their own 'sweet zones'.
  The 1rst course of business is to understand the individual Jfet.
  ..a fairly comprehensive topic [pages that come to mind are located at GEO and Fetzer Valve [ROG.