JFET buffer and more

[Gus]

A text book JFET buffer
It has an input capacitive voltage divider
and a low-pass filter to remove some highs if needed.  I would keep R3 if not using C7 and C5and reduce it to maybe 4.7K
Screen shot from a LT spice sim
Notes on the image to help adjust select parts and for others to sim.


I would use film caps for all but C4

Not built yet

Have fun

[slacker]

Looks interesting. If you don't mind, what's the purpose of C4 and taking the output from junction of R1 and R2, or what's that arrangement called and I'll look it up myself.

[Gus]

http://www.vishay.com/docs/70595/70595.pdf

The simmed circuit is close to a Schoeps circuit

[Gus]

I even left stuff in the sim/schematic to help tune the circuit and select the JFET.

[sault]

@Slacker - that arrangement is called "gate feedback". Look at page 7 of AN102, "Jfet Biasing Characteristics". (Gus posted a link to it below)


C4 would work with R1 to bypass AC and increase gain. It's a little larger than strictly necessary (R1 || C4 = < 1hz), it could be easily as low as 10 uF and still be just fine. The R1 || C4 is essentially a high-pass, in other words, so 910 || 10uF = 17-ish hz which is still under the lowest frequency you're going to hear anyways.

R9 is bigger than it needs to be, in my opinion, but as Jack Orman notes at http://www.muzique.com/lab/buffers.htm, since there isn't any real gain happening (gain with a buffer is always less than 1), the 10M wouldn't really contribute much in the way of Johnson noise, so no harm done.

R3, C5, C7, and R10 aren't strictly needed (R10 is only for the purpose of the simulation though, right?). Having the R3 || C7 lowpass to help cut some of the higher frequencies is nice, though.

The odd thing I'm seeing is that according to the datasheet I'm looking at, the max Idss for a 2N5484 is only 5 mA....

http://www.fairchildsemi.com/ds/MM/MMBF5484.pdf


Saul t

[PRR]

> max Idss for a 2N5484 is only 5 mA....

Gus' note says to bias for 3.9V across 3.9K.... 1mA. So whether Idss(max) is 6.6 or 5, no matter, it will do 1mA.

> 10M wouldn't really contribute much in the way of Johnson noise

Essentially none: its thermal hiss is bypassed by source capacitance (and 300pF pad). 1KHz to 10KHz, just the 300pFd acts as 530K to 53K, a heavy load on a 10Meg source.

And bigger R9 is better (existing C bypasses it more). In a mike-head you want the R9 as big as possible until you run into grid current: 200Meg for tubes, GigaOhms for JFETs. With piezos we have lots more C so we don't have to get that crazy (teflon standoffs and acetone flush).

Yes, hiss may be significant if the input is open-circuit.... don't do that! Anyway in real rooms, hiss would not be audible behind the BUZZZZZ that a hi-hi-Z line catches from room power lines.

> since there isn't any real gain happening

Actually, because R9 returns to source via C4, hiss in R9 is levered by R2*Gm, essentially the gain of the stage when used grounded-source (30-something).

> C4 ...a little larger than strictly necessary (R1 || C4 = < 1hz), it could be easily as low as 10 uF

Gus is bootstrapping. He wants gain VERY-VERY close to unity. Bootstrapping is about leverage. A small slip of gain is a large slip in input impedance. Even another 100 ohms matters. C4 reactance should be under 100 ohms at the lowest frequency of interest. Taking that as 20Hz leads to 100uFd. 82Hz says 27uFd might be OK.... but the cap rating is barely 1 Volt, low-volt caps are cheap, in one-off quantity more picking-fee than actual part cost.... 220uFd has little downside.

And bootstrapping is a lot like a phase-shift oscillator. It is only two poles so it won't sing. But if the two poles are close, it sure can ring. Or rather "hooomm": typically a decade or so below the audio band. In phono preamps it can bump-up at 33rpm warp rate (0.55Hz) and cause very mystifying trouble. I have used 3,000uFd in fairly similar circumstances just to get one pole two+ decades away from the other.

I do wonder why bootstrap. Two 100Meg resistors could bias the gate (any temperature you could play in, the gate leakage would not offset enough to matter) and give 49Meg input, which would not load 300pFd down to 11Hz. Good enuff for most musical purposes. And essentially eliminates the trim, the main bane of battery FET designs.

I do wonder why _both_ C3 and C5, but perhaps Gus will explain his reasons.

[Gus]

Good point about the 2N5484.  I simmed a test circuit in lt spice to check the IDSS of the jfets at different drain to source voltages.  The LT spice 2N5484 "tests" at about 6.6ma IDSS at 9DC D to S and 6.4 at 5VDC D to S and the 2N3819 about 11ma at about 9VDC.  Tested  parameters might be different.

PRR is correct C5 is not needed it was a mistake

Yes there are other Piezo buffer circuits one can build.  One could build a number of different JFET and JFET BJT buffers or a tube CF. 

The point of this circuit is more about the capacitive voltage divider at the input to keep the circuit from clipping

Piezo C2 capacitance and cap pad/voltage divider C1 are guesses



Change the voltage to check the IDSS at different voltages  D to S in the JFET models LT spice uses

[sault]

When I saw "piezo", I interpreted it as a part of the testing circuitry, ie, C2 and R10 are part of the sim around the circuit, not a part of the circuit itself. I can see that designing for a piezo element of a record player has design considerations that I hadn't understood.

C4 reactance should be under 100 ohms at the lowest frequency of interest. Taking that as 20Hz leads to 100uFd. 82Hz says 27uFd might be OK.... but the cap rating is barely 1 Volt, low-volt caps are cheap, in one-off quantity more picking-fee than actual part cost.... 220uFd has little downside.

This is probably going to come across as a bit of a thick question, but why would we be looking at the reactance of C4 solely instead of treating it as an R-C filter in parallel with R1? I arrived at 10uF based on that assumption, the same reasoning that I would normally use in a common-source circuit like the Fetzer valve.

After a bit of thought...

910 Ω || 10 uF  =  17.48 hz
Xc of 10 uF at 17.48 hz = about 910 Ω
910 Ω  || 910 Ω = 455 Ω ,  or half-power... ie, -3 db  (the RC filter corner frequency roll-off)

So in a situation like this, I should be aiming for far less attenuation at my lowest frequency of interest than -3 db?


I was going into this thinking "guitar buffer", but it really does change the rules if its for a record player. Man, I love/hate being wrong. Sorry Gus if I came off as overly critical, it was due to a misunderstanding on my part!


Saul t

[rnfr]

Good point about the 2N5484.  I simmed a test circuit in lt spice to check the IDSS of the jfets at different drain to source voltages.  The LT spice 2N5484 "tests" at about 6.6ma IDSS at 9DC D to S and 6.4 at 5VDC D to S and the 2N3819 about 11ma at about 9VDC.  Tested  parameters might be different.

PRR is correct C5 is not needed it was a mistake

Yes there are other Piezo buffer circuits one can build.  One could build a number of different JFET and JFET BJT buffers or a tube CF.  

The point of this circuit is more about the capacitive voltage divider at the input to keep the circuit from clipping

Piezo C2 capacitance and cap pad/voltage divider C1 are guesses



Change the voltage to check the IDSS at different voltages  D to S in the JFET models LT spice uses

just to be clear- what would cause clipping with a piezo?  don't they have extremely low output?  I've never dealt with them before.



edit:  so they have a higher output voltage, and high output impedance?  would this buffer then be a good candidate at the end of a circuit, say after a distortion stage, before output?  sorry, I'm just trying to figure out what other situations bootstrapping a FET buffer would make sense.  I was always under the impression that the high inZ of FETs made bootstrapping unnecessary, but if they can reduce clipping due to high Vin levels, I could definitely find a place for one.  thanks Gus, always enlightening.  

[PRR]

> I interpreted it as a part of the testing circuitry.... part of the sim around the circuit, not a part of the circuit itself

It could be clearer. (I have found that you can never be clear enough; someone will always get puzzled.)

> why would we be looking at the reactance of C4 solely instead of treating it as an R-C filter in parallel with R1?

It takes a chalkboard and three hands to illustrate this bootstrap.

R1 matters very little because.... hmmmm. Skip that.

The main thing is that C4 R2 are a high-pass.

Assume the JFET has infinite transconductance. (It does not, and we'll have to re-visit this point.)

If signal gets through 99%, then the value of R9 (also Cgs) is multiplied by 100. WOW!

If signal gets through 90%, times 10. Good.

If signal gets through 70% (-3db), R9 is multiplied by 3 (70.7% gives 3.4X). Ho-hum. Nice, but there may be other ways to get an X3 advantage. (In this particular case, 33Meg will work at R9. OTOH 33Meg may be special-order, 220uFd may be rolling around the bench.)

You do have a point. Transconductance will be less than infinite. I won't open data or sim, just guess we can approximate a common JFET at 1mA as equivalent to 500-1,000 ohm source impedance. So the forward gain from gate to source is maybe (910+3K9)/(500+910+3K9) or 0.9. Best we can do is a 10X bootstrapping factor. However R9 must return below R2 to get the DC right, and without C4 the gain to R2 is 0.73, 3.7X bootstrapping factor.

So a "mere" 910 ohm difference has dropped input Z from 100Meg to 37Meg.

If we "need" 100Meg, or anything close, we need much-less than 900 ohms reactance in C4 at the lowest frequency of interest, (for piezo, the LOWest frequency we wish to recover).

I suspect either one is entirely satisfactory for music. As Gus suggests, this is "have fun, not built yet". You may find other values which work, maybe work better, maybe work the same cheaper, etc.

> a piezo element of a record player has design considerations that I hadn't understood.

Yes, and rarely well-considered. But also totally antiquated.

No, many-many people own Barcus-Berry (the original) or other commercial piezo instrument pickups, or adapt piezo buzzer-elements from toys and appliances.

In Gus' plan, C2 is a simulated piezo, C1 is a clever pad which gives broad-band reduction of piezo voltage and impedance. A VERY useful trick.

> what would cause clipping with a piezo?  don't they have extremely low output?

As with ANY pickup, output depends how you use them.

Magnetic (conventional) guitar pickups must not touch the string, large gap, lower output.

And part of the problem is that all guitar amps are MADE for the standard magnetic pickups and their weaker outputs.

But you can jam a slim piezo between bridge and body. There is a LOT of contact force here, and a lot of leverage between limp string and substantial body. While piezos are rarely installed for MAXimum output (they need to bend), even a "flat" installation typically gives high voltage, and decent current in treble, but puny current in bass. If loaded with 100K-1Meg inputs suitable for magnetic pickups, you tend to get brittle (clipped) highs and weak bass.

> I was always under the impression that the high inZ of FETs made bootstrapping unnecessary

Very rarely necessary. I do not think there is a technical justification for that aspect of Gus' plan. I would propose other values, except I generally HATE piezos.

[Gus]

I posted this SF type circuit kind of to show there are different SF follower circuits one can build.

The Vishay link
http://www.vishay.com/docs/70595/70595.pdf       
shows other followers

[sault]

I really do appreciate you posting it, it's sparked a very educational discussion for me.

I never knew that you might need more than 10M input impedance... ever, really. It's good to know that  A) I'm wrong,  B) what times you might need to,  and C) that it's possible at all.

I'll need a little bit of time to redigest everything, but thank you Gus and PRR for helping me out on this one!


Saul t

[JRay]

Slightly old but good thread!!

I wonder if you guys can help. I love the idea of simple FET input buffer stages, no idea why, they just seem simpler more elegant that plonking an opamp in the circuit.

Here is what I intend to use as a FET buffer for my mag pickup and this circuit provides an input Z of 1.1MEG (R1 and R3 in parallel). This circuit seems to provide very low distortion and high headroom and is for all intents and purposes unity gain. Output Z is around 500 - 600 ohms. All you have to do is match the JFETs Idss as closely as you can, say out of a batch of ten or so. Sounds extremely clean.



What do you guys think of this circuit as a buffer, do you see any problems or short comings with it?

[PRR]

> match the JFETs Idss as closely as you can

I've fought such a scheme in a HeathKit DC-coupled input. JFETs don't match that good. I ended up using a $20 chip (worth about $0.69 today).

However your plan is not DC-coupled, offsets don't matter. The key thing is to be sure your J1 has higher Idss than your J2, so J1 does not have to forward-bias. Or put 500 ohms under J2 to reduce its effective Idss, then you don't have to match.

I will speculate that J2 could as well be a 5K-10K resistor. Gain could fall from 0.98 to 0.9, but in audio we tolerate small 10% changes (we have a knob somewhere to bring it up).

D1 seems nearly pointless. J1's gate diode does the same thing. (A JFET is a diode with two contacts at the "bar end", and incidentally a very good small diode.) J1 gate junction is rated a whopping 50mA. Yes your D1 may be rated 100mA, but we hope never to have anywhere near these levels. On an accident-prone stage, you can't just use bigger protecting diodes; there is always a bigger source to mis-plug to. The usual protection starts with some resistance in front, so that reasonable voltages produce tolerable currents. The standard guitar input uses 34K to block AM-radio. If we fear 120V sources (guitar touches horribly bad-grounded PA mike), 120V/30K= 4mA, utterly safe for J201 gate junction. We get in trouble past 1,000V.

D2 also may be redundant. Severe negative inputs will break-down J1 gate diode. If infinite current flows, it overheats melts. But if dissipation is less than device rating, no real harm is done. Let's see... 40V rated so maybe 60V actual, 350mW dissipation, we could flow 6mA. 6mA in the assumed 33K resistor is 200V, we can take 260V with safety.

So just adding 33K at J1 gate reduces RF and protects against >100V sources.

I think you should sport a 33K gate resistor. The diodes are frills but I admit that my time to type is worth more than all the 1N4148s you would ever use.

[FredB]

Ha, capacitive divider!

I had to think about that one for a while.

The higher the frequency, the more it reduces the signal.

Brilliant, it's completely unnecessary for inductive pickups, which self attenuate the highs.  Although for other sensors that increase the signal with frequency, it's very useful.

BTW What are the neighborhood values for the output impedance of a piezo pickup?

[JRay]

Thanks for your very interesting reply Paul.R!
I pinched the 2 JFET buffer config. from the Nelson Pass B1 Buffer preamp here...

http://www.passdiy.com/pdf/B1%20Buffer%20Preamp.pdf

He mentions the need to match the Idss of each FET as closely as possible

The buffer input stage is meant for use with my acoustic guitar pickup, an LR Baggs M1, therefore my aim is for a high fidelity, low noise circuit. I originally started out as you said with a 10K resistor replacing J2 in the schematic, standard JFET buffer ala Jack Orman etc, and this in simulation gave a THD at 1 KHz of just under 0.02% and again as you stated, around -0.6db attenuation. With the 2 JFET config the simulation gave a THD figure of 0.002% and -0.06db attenuation. I doubt very much if the distortion in either case will make much of an audible difference however, it is just the feel good factor of the better distortion figure in the 2 FET conifg, as well as better headroom before clipping. If I add a 500R resistor under J2 as you suggested the distortion increases very slightly. Obviously in SIM land J1 and J2 have identical Idss which is not practical, but I managed to match up the two JFETs I used in the bread board version pretty closely and it sounded great!

As the preamp will be used for gigs reliability is just as important as sound quality (probably even more so!) I read that it is quite easy to blow FETs with static or high voltages on the inputs due to connection errors etc that plague the gigging scene, and hence why I used the diodes on the input.  I had no idea how these diodes actually operated in the circuit, I just pinched the idea of the net as usual! Your knowledge is infinitely larger than mine in these matters and if you feel that more than adequate protection will be provided by  a gate resistor, then this is what I will do, and hopefully also add better RF immunity to boot . Bear in mind that I am on the other side of the pond and so my mains is 240V which would equate to a little above 7mA "fault current" through a 33K input resistor, but as you said this is still not high enough to cause issues . Circuit changes to the below, and I hope this is what you meant by the gate resistor...



Once again thanks for your time and help here, I always find your posts both informative and enjoyable!

[PRR]

> Ha, capacitive divider!
> The higher the frequency, the more it reduces the signal.

No; you are missing important info.....

> What are the neighborhood values for the output impedance of a piezo pickup?

Gus's C2 "capacitance of piezo", 500pFd.

A more accurate model would have some hundreds of ohms series resistance, many million ohms shunt resistance (less in damp weather), lead inductance, some mechanical self-resonance.... but for near any practical audio purpose, a piezo is a capacitor and 500pFd is reasonable for a small piezo.

Gus teaches that you can put 300pFd fixed cap in series to ground, and take the output across the 300pFd. The piezo's internal voltage is divided by 300/(500+300) or 3/8ths... at ALL frequencies(*). The line impedance of the naked piezo is 500pFd, but at the divider tap is is 800pFd, which may be a bit less susceptable to crap.

(*) At ALL frequencies where stray resistances are not similar to the capacitive reactance.

500pFd is:
16Meg at 20Hz
1.6Meg at 200Hz
160K at 2KHz
16K at 20KHz

Therefore the capsule leakage, hundreds of MegOhms, only matters below 2Hz; the hundred-Ohm stray resistance in contacts and leads matters above 1MHz.

However a 1Meg gitar-amp input is significant at 320Hz. This is one reason piezos tend to sound "gutless". We need to go over 5meg amplifier input to get small-loss at the lowest guitar note.

Some larger piezos are over 2,000pFd and will drive bass into a 1Meg input.

[FredB]

I think I got that.  

I originally asked about the output impedance because I simmed the piezo and the cap divider driving a 10M load.  I saw that the frequency response above the low frequency roll off point was flat.  I had presumed that the divider was supposed to roll off the highs to avoid clipping them.   With about 500k added in series with the piezo there was a significant roll off of the highs.  I was wondering what the response curve was suppose to look like.

So the response was suppose to be flat.  I understand the need then to provide enough input impedance to insure sufficient lows are retained, and the cap divider is a kind of impedance transformer to help with noise rejection.  

This actually might be useful to me one day.  If I ever have money again, I want to get a Taylor.  Then I can build an input circuit for it.  

[PRR]

> Nelson Pass B1 Buffer preamp ...He mentions the need to match

"The best performance generally comes from matching the Idss"

Yeah, but look who is talking. A Hi-Fi Guru.

"Below a volt, the distortion comes in at about .0007%"

Yes if you want zero-zero-zero distortion you must null the even-order product by matching the FETs.

Same-batch unmatched JFETs may give 0.01%THD.

A simple resistor-loaded follower could be as high as 0.15%THD for 1V peak with 9V supply (less for typical guitar levels or with higher supply.)

These are quite low. You might hear them (as "congestion") on complex full-orchestra waves, but hardly-at-all on six naked strings.

The un-match and the R-load give some even-order which (for music creation) does more good than harm. (OTOH, Pass is on the reproduction side; he assumes the recording already has all the harmonics the performer/producer felt was best).

Match if you want. I think for our purposes it makes no difference, but it's your time.

[JRay]

The un-match and the R-load give some even-order which (for music creation) does more good than harm. (OTOH, Pass is on the reproduction side; he assumes the recording already has all the harmonics the performer/producer felt was best).

Good point! Do you think then that a single JFET source follower buffer as per Gus's original circuit, producing very slightly more even-order harmonic distortion, would be better even for acoustic guitar, than an ultra low THD circuit like the matched 2 JFET config?  Would the tiny bit of even-order HD give say a little more character? I intend to amplify the output of the buffer with an opamp gain stage  (around 25db) and also a phase inverter so the output polarity can be switched.