FET Phaser Design Help

[Scruffie]

I'm trying to get to grips with phasers a bit better so I thought i'd take a stab at building a simple one up on the breadboard.

So far I have phasing but there's a problem, the sweep seems to rise up fine but then slam down to the bottom rather than going up and down smoothly, the only thing I can think of is one of the FETs is switching on and off abruptly but not really knowing about phaser design, I don't know why.

Here's where i'm at... sorry for the quickly drawn schematic, I know it's not very complete but i'm just trying to get the basics down.



I've tried looking at a few other FET based phaser designs and can't see where i'm going wrong, admittedly I haven't matched the FETs but i've gone through trying different ones and i'm not seeing any massive changes.

Any ideas from you phaser gurus?

[frequencycentral]

It's either your FETs or your LFO. In a two stage design matching is pretty much essential to hear any phasing. You need to know the Vgs of your FETs anyway to match them to your LFO. Changes can be made to the LFO to offset it with respect to vref. Or your vref can be adjustable like the P45/P90.

[Rob Strand]

At the moment you have more of a vibrato.  For a phaser needs an extra 10k between pin 7 and  R5 (10k).  That will form a passive mixer to combine the two halfs.

Try adjusting reducing/adjusting R6 by to see if you can improve the sweep behaviour.   This will adjust the JFET cut-off point.

[Scruffie]

It's either your FETs or your LFO. In a two stage design matching is pretty much essential to hear any phasing. You need to know the Vgs of your FETs anyway to match them to your LFO. Changes can be made to the LFO to offset it with respect to vref. Or your vref can be adjustable like the P45/P90.

At the moment you have more of a vibrato.  For a phaser needs an extra 10k between pin 7 and  R5 (10k).  That will form a passive mixer to combine the two halfs.

Try adjusting reducing/adjusting R6 by to see if you can improve the sweep behaviour.   This will adjust the JFET cut-off point.

Oh I just missed that off the schematic.

Yeah I tried adjusting the V.Ref, it helped a little but not much.

It's either your FETs or your LFO. In a two stage design matching is pretty much essential to hear any phasing. You need to know the Vgs of your FETs anyway to match them to your LFO. Changes can be made to the LFO to offset it with respect to vref. Or your vref can be adjustable like the P45/P90.

I'm hearing Phasing so I probably got lucky with the set, i'm using 2N5457s so... 2.5Vgs, perhaps that's why, haven't matched them to the LFO. I did try a few different adjustable biases, some helped a bit, others not so much, i'll try some other FETs and a new LFO.

Cheers for the help.

[Fender3D]

You'll need a cap from common gate CV and V.ref also.
It will smooth the way FETs work
(as in Pxx)

[Gurner]

To my eyes, your 2nd opamp stage is wired wrong ....the connection to pins 5 & 6 should be crossed pin for pin (ie on your first stage the opamp's -ve pin is at the top, but on the 2nd stage the opamp's +ve pin is at the top   ....the lfo controlled fet leg should be going to the opamp's +ve input on both stages)

[Rob Strand]

I can suggest two other things:

- the first is to change the 120k's across the JFET D and S to 22k or so.
  This prevents excessive resistance changes in the JFETs, beyond
  about 30k or so the all-pass resistance won't track well.

- as an experiment add a 220k (100k to 470k) resistor from the gate to either Vref or to ground,
  then adjust R6 for best sound afterwards.  What this is doing is decreasing
  the swing from the LFO.

[Scruffie]

To my eyes, your 2nd opamp stage is wired wrong ....the connection to pins 5 & 6 should be crossed pin for pin (ie on your first stage the opamp's -ve pin is at the top, but on the 2nd stage the opamp's +ve pin is at the top   ....the lfo controlled fet leg should be going to the opamp's +ve input on both stages)

Sorry! Drew that wrong as well, I just knocked it together as a quick example, it's connected the other way in reality.

I'm having a bit more luck now, changed the LFO and while it's still not working right, it did show that alot of the problem was there.

I can suggest two other things:

- the first is to change the 120k's across the JFET D and S to 22k or so.
  This prevents excessive resistance changes in the JFETs, beyond
  about 30k or so the all-pass resistance won't track well.

- as an experiment add a 220k (100k to 470k) resistor from the gate to either Vref or to ground,
  then adjust R6 for best sound afterwards.  What this is doing is decreasing
  the swing from the LFO.

I actually did add some 10ks to 100k from the Gate to V.Ref, that did help some, but not enough, i'm just gunna try out some new LFOs.

I'll try altering the 120ks too.

[R.G.]

See some comments in the thread I just started on LFOs.

[Scruffie]

See some comments in the thread I just started on LFOs.

I always knew FETs were funny in Tremolos but for some reason it didn't occur to me they might not play nice in a phaser too...

Anyway, fixed the problem now! Found a new LFO that works, that's all that was needed.

Cheers for the tips though guys, i'll remember them for if I play with phasers more... still not sure how keen I am on them.